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[SOL] Better sBPFv1 sign extension #103

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[SOL] Better sBPFv1 sign extension #103

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13 changes: 13 additions & 0 deletions llvm/lib/Target/SBF/SBFISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1023,6 +1023,19 @@ SBFTargetLowering::EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB,
BuildMI(BB, DL, TII.get(SBF::MOV_32_64), PromotedReg0).addReg(Reg);
return PromotedReg0;
}

if (Subtarget->isSolana()) {
const TargetRegisterClass *RC32 = getRegClassFor(MVT::i32);
Register Reg0 = RegInfo.createVirtualRegister(RC32);
Register PromotedReg0 = RegInfo.createVirtualRegister(RC);
BuildMI(BB, DL, TII.get(SBF::ADD_ri_32), Reg0).addReg(Reg).addImm(0);
BuildMI(BB, DL, TII.get(SBF::SUBREG_TO_REG), PromotedReg0)
.addImm(0)
.addReg(Reg0)
.addImm(SBF::sub_32);
return PromotedReg0;
}

Register PromotedReg0 = RegInfo.createVirtualRegister(RC);
Register PromotedReg1 = RegInfo.createVirtualRegister(RC);
Register PromotedReg2 = RegInfo.createVirtualRegister(RC);
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2 changes: 1 addition & 1 deletion llvm/lib/Target/SBF/SBFInstrInfo.td
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Expand Up @@ -969,7 +969,7 @@ def : Pat<(SBFWrapper tglobaladdr:$in),


def : Pat<(i64 (sext GPR32:$src)),
(SRA_ri (SLL_ri (MOV_32_64 GPR32:$src), 32), 32)>;
(SUBREG_TO_REG (i64 0), (ADD_ri_32 GPR32:$src, 0), sub_32)>;

def : Pat<(i64 (zext GPR32:$src)), (MOV_32_64 GPR32:$src)>;

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63 changes: 63 additions & 0 deletions llvm/lib/Target/SBF/SBFMIPeephole.cpp
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Expand Up @@ -185,6 +185,69 @@ bool SBFMIPeephole::eliminateZExtSeq() {
}

// Eliminate the 32-bit to 64-bit zero extension sequence when possible.
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This is in the wrong place - This deals with sign extension, not zero extension

// (new MOV32/ADD32)
//
// w0@1 := SUB_ri w0@0, 1 # user instruction that sign-extends
// w0@2 := ADD_ri w0@1, 0 # sign extend inserted by SBPFISelLowering
// r0@3 := SUBREG_TO_REG 0, w0@2, sub_32
//
// to
//
// w0@1 := SUB_ri w0@0, 1 # user instruction that sign-extends
// r0@3 := SUBREG_TO_REG 0, w0@1, sub_32
if (MI.getOpcode() == SBF::SUBREG_TO_REG &&
MI.getOperand(1).getImm() == 0 &&
MI.getOperand(3).getImm() == SBF::sub_32) {
Register DstReg = MI.getOperand(0).getReg();
Register SextReg = MI.getOperand(2).getReg();
MachineInstr *SextMI = MRI->getVRegDef(SextReg);

LLVM_DEBUG(dbgs() << "Starting SUBREG_TO_REG found:\n");
LLVM_DEBUG(MI.dump());

if (!SextMI || SextMI->isPHI() ||
SextMI->getOpcode() != SBF::ADD_ri_32 ||
SextMI->getOperand(2).getImm() != 0)
continue;

LLVM_DEBUG(dbgs() << " ADD32 REG, 0 found:\n");
LLVM_DEBUG(SextMI->dump());

Register UserReg = SextMI->getOperand(1).getReg();
MachineInstr *UserMI = MRI->getVRegDef(UserReg);
if (!UserMI || UserMI->isPHI())
continue;

// Check if source register of "ADD32 REG, 0" is already in sign
// extended form.
switch (UserMI->getOpcode()) {
case SBF::ADD_ri_32:
case SBF::SUB_ri_32:
case SBF::MUL_ri_32:
break;
default:
continue;
}

LLVM_DEBUG(dbgs() << " Sign-extending instruction found:\n");
LLVM_DEBUG(UserMI->dump());

BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(SBF::SUBREG_TO_REG), DstReg)
.addImm(0)
.addReg(UserReg)
.addImm(SBF::sub_32);
SextMI->eraseFromParent();

// Can't erase the SUBREG_TO_REG in it's own iteration.
// Mark it to ToErase, and erase in the next iteration.
ToErase = &MI;
ZExtElemNum++;
Eliminated = true;
break;
}

// Eliminate the 32-bit to 64-bit zero extension sequence when possible.
// (old SLL/SRL)
//
// MOV_32_64 rB, wA
// SLL_ri rB, rB, 32
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6 changes: 2 additions & 4 deletions llvm/test/CodeGen/SBF/32-bit-subreg-peephole.ll
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Expand Up @@ -73,8 +73,7 @@ define dso_local i64 @select_s(i32 %a, i32 %b, i64 %c, i64 %d) local_unnamed_add
entry:
%cmp = icmp sgt i32 %a, %b
%c.d = select i1 %cmp, i64 %c, i64 %d
; CHECK: lsh64 r{{[0-9]+}}, 32
; CHECK-NEXT: arsh64 r{{[0-9]+}}, 32
; CHECK: add32 w{{[0-9]+}}, 0
; CHECK: {{jslt|jsgt}} r{{[0-9]+}}, r{{[0-9]+}},
ret i64 %c.d
}
Expand Down Expand Up @@ -117,8 +116,7 @@ entry:
%cmp = icmp sgt i32 %call, 6
; The shifts can't be optimized out because %call comes from function call
; return i32 so the high bits might be invalid.
; CHECK: lsh64 r{{[0-9]+}}, 32
; CHECK-NEXT: arsh64 r{{[0-9]+}}, 32
; CHECK: add32 w{{[0-9]+}}, 0
%cond = zext i1 %cmp to i32
; CHECK: {{jslt|jsgt}} r{{[0-9]+}}, {{[0-9]+}},
ret i32 %cond
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20 changes: 8 additions & 12 deletions llvm/test/CodeGen/SBF/atomics_sbf.ll
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Expand Up @@ -181,12 +181,10 @@ entry:

; CHECK-LABEL: test_min_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: mov64 r4, r0
; CHECK: lsh64 r4, 32
; CHECK: arsh64 r4, 32
; CHECK: mov32 r5, w2
; CHECK: lsh64 r5, 32
; CHECK: arsh64 r5, 32
; CHECK: mov32 w4, w0
; CHECK-NEXT: add32 w4, 0
; CHECK: mov32 w5, w2
; CHECK-NEXT: add32 w5, 0
; CHECK: mov32 w3, w0
; CHECK: jslt r4, r5, LBB16_2
; CHECK: mov32 w3, w2
Expand All @@ -211,12 +209,10 @@ entry:

; CHECK-LABEL: test_max_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: mov64 r4, r0
; CHECK: lsh64 r4, 32
; CHECK: arsh64 r4, 32
; CHECK: mov32 r5, w2
; CHECK: lsh64 r5, 32
; CHECK: arsh64 r5, 32
; CHECK: mov32 w4, w0
; CHECK-NEXT: add32 w4, 0
; CHECK: mov32 w5, w2
; CHECK-NEXT: add32 w5, 0
; CHECK: mov32 w3, w0
; CHECK: jsgt r4, r5, LBB18_2
; CHECK: mov32 w3, w2
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9 changes: 4 additions & 5 deletions llvm/test/CodeGen/SBF/loop-exit-cond.ll
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Expand Up @@ -49,11 +49,10 @@ for.cond: ; preds = %for.inc, %if.then
%cmp1 = icmp slt i32 %2, %3
br i1 %cmp1, label %for.body, label %for.cond.cleanup

; CHECK: mov32 r[[LEN:[0-9]+]], w1
; CHECK: add32 w[[IDX32:[0-9]+]], 1
; CHECK: mov64 r[[IDX:[0-9]+]], r[[IDX32:[0-9]+]]
; CHECK: lsh64 r[[IDX:[0-9]+]], 32
; CHECK: arsh64 r[[IDX:[0-9]+]], 32
; CHECK: mov32 w[[LEN32:[0-9]+]], w1
; CHECK: add32 w[[IDX:[0-9]+]], 1
; CHECK: mov32 w[[LEN:[0-9]+]], w[[LEN32]]
; CHECK: add32 w[[LEN]], 0
; CHECK-NEXT: jslt r[[IDX]], r[[LEN]],

for.cond.cleanup: ; preds = %for.cond
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