ansys · svandenb-dev · Oct 24, 2023 · Oct 24, 2023 · Oct 24, 2023 · Oct 24, 2023
diff --git a/doc/source/Resources/advanced_circuit_port_creation.PNG b/doc/source/Resources/advanced_circuit_port_creation.PNG
diff --git a/doc/source/Resources/clipped_layout.png b/doc/source/Resources/clipped_layout.png
diff --git a/doc/source/Resources/create_circuit_ports_on_component.PNG b/doc/source/Resources/create_circuit_ports_on_component.PNG
diff --git a/doc/source/Resources/create_coaxial_port_on_component.png b/doc/source/Resources/create_coaxial_port_on_component.png
diff --git a/doc/source/Resources/layout_nets_after_cutout.png b/doc/source/Resources/layout_nets_after_cutout.png
diff --git a/doc/source/Resources/layout_plot_all_nets.png b/doc/source/Resources/layout_plot_all_nets.png
diff --git a/doc/source/Resources/layout_plot_gnd_nets.png b/doc/source/Resources/layout_plot_gnd_nets.png
diff --git a/doc/source/Resources/stackup.png b/doc/source/Resources/stackup.png
diff --git a/doc/source/Scripts_resources/SI/add_simulation_setup.py b/doc/source/Scripts_resources/SI/add_simulation_setup.py
@@ -0,0 +1,39 @@
+import pyaedt
+from pyaedt import Edb, Hfss3dLayout
+
+# Ansys release version
+desktop_version = "2023.2"
+
+#download and copy the layout file from examples
+temp_folder = pyaedt.generate_unique_folder_name()
+targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder)
+
+# loading EDB
+edbapp = Edb(edbpath=targetfile, edbversion=desktop_version)
+
+simple_hfss_setup = edbapp.create_hfss_setup("MySimpleSetup")
+simple_hfss_setup.set_solution_single_frequency(frequency="5GHz", max_num_passes=30, max_delta_s=0.05)
+simple_hfss_setup.add_frequency_sweep(name="MySweep", frequency_sweep=[["linear scale", "0GHz", "10GHz", "0.01GHz"]])
+
+multi_freq_setup = edbapp.create_hfss_setup("MyMultiFreqSetup")
+multi_freq_setup.set_solution_multi_frequencies(frequencies=["5GHz", "7GHz", "10GHz"], max_num_passes=30, max_delta_s=0.02)
+multi_freq_setup.add_frequency_sweep(name="MySweep", frequency_sweep=[["linear scale", "0GHz", "20GHz", "0.01GHz"]])
+
+broad_band_sweep = edbapp.create_hfss_setup("MyBroadbandSetup")
+broad_band_sweep.set_solution_broadband(low_frequency="5GHz", high_frequency="10GHz", max_num_passes=20, max_delta_s=0.01)
+broad_band_sweep.add_frequency_sweep(name="MySweep", frequency_sweep=[["linear scale", "0GHz", "20GHz", "0.01GHz"]])
+
+# adding frequency sweeps
+multi_freq_sweep_setup = edbapp.create_hfss_setup("MyMultiFrequencySweepSetup")
+multi_freq_sweep_setup.set_solution_single_frequency(frequency="5GHz", max_num_passes=30, max_delta_s=0.02)
+multi_freq_sweep_setup.add_frequency_sweep(frequency_sweep=[["linear count", "0", "1kHz", 1],
+                                                ["log scale", "1kHz", "0.1GHz", 10],
+                                                ["linear scale", "0.1GHz", "10GHz", "0.1GHz"],
+                                                ])
+
+# save and close project
+edbapp.save_edb()
+edbapp.close_edb()
+hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version)
+hfss.release_desktop(close_desktop=False, close_projects=False)
+
diff --git a/doc/source/Scripts_resources/SI/advanced_circuit_port_creation.py b/doc/source/Scripts_resources/SI/advanced_circuit_port_creation.py
@@ -0,0 +1,33 @@
+import pyaedt
+from pyaedt import Edb, Hfss3dLayout
+from pyaedt.generic.constants import SourceType
+
+# Ansys release version
+desktop_version = "2023.2"
+
+# download and copy the layout file from examples
+temp_folder = pyaedt.generate_unique_folder_name()
+targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder)
+
+# loading EDB
+edbapp = Edb(edbpath=targetfile, edbversion=desktop_version)
+
+signal_nets = ["DDR4_DQ0", "DDR4_DQ1", "DDR4_DQ2", "DDR4_DQ3", "DDR4_DQ4", "DDR4_DQ5", "DDR4_DQ6", "DDR4_DQ7"]
+reference_nets = ["GND"]
+
+# processing cutout
+edbapp.cutout(signal_list=signal_nets, reference_list=reference_nets, expansion_size=0.01)
+
+# creating ports on specific component pins
+component = edbapp.components["U1"]
+for net in signal_nets:
+    pins = [pin for pin in list(component.pins.values()) if pin.net_name == net]
+    for pin in pins:
+        ref_pins = pin.get_reference_pins(reference_net="GND", search_radius=5e-3, max_limit=3, component_only=True)
+        edbapp.components.create_port_on_pins(refdes="U1", pins=pin, reference_pins=ref_pins)
+
+# save and close project
+edbapp.save_edb()
+edbapp.close_edb()
+hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version)
+hfss.release_desktop(close_desktop=False, close_projects=False)
diff --git a/doc/source/Scripts_resources/SI/clipping_design.py b/doc/source/Scripts_resources/SI/clipping_design.py
@@ -0,0 +1,29 @@
+import pyaedt
+from pyaedt import Edb, Hfss3dLayout
+
+# Ansys release version
+desktop_version = "2023.2"
+
+#download and copy the layout file from examples
+temp_folder = pyaedt.generate_unique_folder_name()
+targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder)
+
+# loading EDB
+edbapp = Edb(edbpath=targetfile, edbversion=desktop_version)
+
+# selecting signal nets to evaluate the extent for clipping the layout
+signal_nets = ["DDR4_DQ0", "DDR4_DQ1", "DDR4_DQ2", "DDR4_DQ3", "DDR4_DQ4", "DDR4_DQ5", "DDR4_DQ6", "DDR4_DQ7"]
+# at least one reference net must be inclulded. Reference nets are included in the design but clipped.
+reference_nets = ["GND"]
+# defining the expansion factor. The value gives the distance for evaluating the cutout extent. Here we define a cutout
+expansion = 0.01  # 1cm in this case
+# processing cutout
+edbapp.cutout(signal_list=signal_nets, reference_list=reference_nets, expansion_size=expansion)
+# save and close project
+edbapp.save_edb()
+edbapp.close_edb()
+# opening resulting in AEDT to visualize the resulting project.
+hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version)
+# After opening AEDT with PyAEDT, if you want to be able to close manually the project you have to release
+# AEDT from PyAEDT.
+hfss.release_desktop(close_desktop=False, close_projects=False)
diff --git a/doc/source/Scripts_resources/SI/create_hfss_excitation_ports.py b/doc/source/Scripts_resources/SI/create_hfss_excitation_ports.py
@@ -0,0 +1,30 @@
+import pyaedt
+from pyaedt import Edb, Hfss3dLayout
+
+# Ansys release version
+desktop_version = "2023.2"
+
+#download and copy the layout file from examples
+temp_folder = pyaedt.generate_unique_folder_name()
+targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder)
+
+# loading EDB
+edbapp = Edb(edbpath=targetfile, edbversion=desktop_version)
+
+signal_nets = ["DDR4_DQ0", "DDR4_DQ1", "DDR4_DQ2", "DDR4_DQ3", "DDR4_DQ4", "DDR4_DQ5", "DDR4_DQ6", "DDR4_DQ7"]
+reference_nets = ["GND"]
+
+# processing cutout
+edbapp.cutout(signal_list=signal_nets, reference_list=reference_nets, expansion_size=0.01)
+
+if not edbapp.components.create_port_on_component(component="U1", net_list=signal_nets, reference_net="GND"):
+    edbapp.logger.error("Failed to create ports on component U1")
+if not edbapp.components.create_port_on_component(component="U15", net_list=signal_nets, reference_net="GND"):
+    edbapp.logger.error("Failed to create port on component U15")
+
+
+# save and close project
+edbapp.save_edb()
+edbapp.close_edb()
+hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version)
+hfss.release_desktop(close_desktop=False, close_projects=False)
diff --git a/doc/source/Scripts_resources/SI/create_siwave_excitation_ports.py b/doc/source/Scripts_resources/SI/create_siwave_excitation_ports.py
@@ -0,0 +1,38 @@
+import pyaedt
+from pyaedt import Edb, Hfss3dLayout
+from pyaedt.generic.constants import SourceType
+
+# Ansys release version
+desktop_version = "2023.2"
+
+#download and copy the layout file from examples
+temp_folder = pyaedt.generate_unique_folder_name()
+targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder)
+
+# loading EDB
+edbapp = Edb(edbpath=targetfile, edbversion=desktop_version)
+
+signal_nets = ["DDR4_DQ0", "DDR4_DQ1", "DDR4_DQ2", "DDR4_DQ3", "DDR4_DQ4", "DDR4_DQ5", "DDR4_DQ6", "DDR4_DQ7"]
+reference_nets = ["GND"]
+
+# processing cutout
+edbapp.cutout(signal_list=signal_nets, reference_list=reference_nets, expansion_size=0.01)
+
+if not edbapp.components.create_port_on_component(component="U1", net_list=signal_nets,
+                                                  reference_net="GND",
+                                                  port_type=SourceType.CircPort,
+                                                  ):
+    edbapp.logger.error("Failed to create ports on component U1")
+if not edbapp.components.create_port_on_component(component="U15",
+                                                  net_list=signal_nets,
+                                                  reference_net="GND",
+                                                  port_type=SourceType.CircPort,
+                                                  ):
+    edbapp.logger.error("Failed to create port on component U15")
+
+
+# save and close project
+edbapp.save_edb()
+edbapp.close_edb()
+hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version)
+hfss.release_desktop(close_desktop=False, close_projects=False)
diff --git a/doc/source/Scripts_resources/SI/editing_layer_stackup.py b/doc/source/Scripts_resources/SI/editing_layer_stackup.py
@@ -0,0 +1,40 @@
+import pyaedt
+from pyaedt import Edb, Hfss3dLayout
+
+# Ansys release version
+desktop_version = "2023.2"
+
+#download and copy the layout file from examples
+temp_folder = pyaedt.generate_unique_folder_name()
+targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder)
+
+# loading EDB
+edbapp = Edb(edbpath=targetfile, edbversion=desktop_version)
+
+# ploting layer stackup in matplotlib
+edbapp.stackup.plot()
+
+# retrieving signal layers name
+signal_layers = list(edbapp.stackup.signal_layers.keys())
+
+# selecting top layer
+top_layer = edbapp.stackup.signal_layers[signal_layers[0]]
+
+# Stackup total thickness
+layout_stats = edbapp.get_statistics()
+layout_stats.stackup_thickness
+
+# setting all signal layers thickness to 20um
+for layer_name, layer in edbapp.stackup.signal_layers.items():
+    layer.thickness = "20um"
+
+edbapp.materials.add_material(name="MyMaterial", permittivity=4.35, dielectric_loss_tangent=2e-4)
+edbapp.materials.add_material(name="MyMetal", conductivity=1e7)
+for layer in list(edbapp.stackup.dielectric_layers.values()):
+    layer.material = "MyMaterial"
+for layer in list(edbapp.stackup.signal_layers.values()):
+    layer.material = "MyMetal"
+edbapp.materials.add_material(name="SolderMask", permittivity=3.8, dielectric_loss_tangent=1e-3)
+edbapp.stackup.add_layer(layer_name="Solder_mask", base_layer="1_Top", thickness="200um", material="SolderMask")
+
+
diff --git a/doc/source/Scripts_resources/SI/hfss_simulation_setup.py b/doc/source/Scripts_resources/SI/hfss_simulation_setup.py
diff --git a/doc/source/Scripts_resources/SI/layout_import.py b/doc/source/Scripts_resources/SI/layout_import.py
@@ -0,0 +1,39 @@
+import pyaedt
+from pyaedt import Edb, Hfss3dLayout
+
+# Ansys release version
+desktop_version = "2023.2"
+
+#download and copy the layout file from examples
+temp_folder = pyaedt.generate_unique_folder_name()
+targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder)
+
+# loading EDB
+edbapp = Edb(edbpath=targetfile, edbversion=desktop_version)
+
+# Some layout statistics
+stats = edbapp.get_statistics()
+
+# When edb is loaded, we can access all layout information
+nets = edbapp.nets
+
+# net list
+nets.netlist
+
+# power nets
+nets.power
+
+# Getting components from specific net
+nets.power["GND"].components
+
+# Getting pins from components
+edbapp.components["U9"].pins
+
+# Getting pins from components connected to given net
+u9_gnd_pins = [pin for pin in list(edbapp.components["U9"].pins.values()) if pin.net_name == "GND"]
+
+# Plotting layout in matplotlib
+edbapp.nets.plot(None)
+
+# plotting specific net
+edbapp.nets.plot("GND")
diff --git a/doc/source/Scripts_resources/SI/post_processing.py b/doc/source/Scripts_resources/SI/post_processing.py
diff --git a/doc/source/Scripts_resources/SI/run_analysis.py b/doc/source/Scripts_resources/SI/run_analysis.py
diff --git a/doc/source/Signal Integrity/index.rst b/doc/source/Signal Integrity/index.rst
@@ -0,0 +1,10 @@
+==================================================
+High frequency channel extraction workflow example
+==================================================
+
+This section describes an automated workflow using PyANSYS-EDB for high frequency channel extraction:
+
+.. toctree::
+   :maxdepth: 2
+
+
diff --git a/doc/source/User_guide/cutout.rst b/doc/source/User_guide/cutout.rst
@@ -0,0 +1,40 @@
+Clipping layout
+===============
+Because most of the time only a specific part of a layout must be simulated, clipping the design
+needs to be performed to reduce computer resources and speed up simulation. This section describes
+how to clip a design based on nets selection.
+
+.. code:: python
+    import pyaedt
+    from pyedb import Edb, Hfss3dLayout
+
+    # Ansys release version
+    desktop_version = "2023.2"
+
+    #download and copy the layout file from examples
+    temp_folder = pyaedt.generate_unique_folder_name()
+    targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder)
+
+    # loading EDB
+    edbapp = Edb(edbpath=targetfile, edbversion=desktop_version)
+
+    # selecting signal nets to evaluate the extent for clipping the layout
+    signal_nets = ["DDR4_DQ0", "DDR4_DQ1", "DDR4_DQ2", "DDR4_DQ3", "DDR4_DQ4", "DDR4_DQ5", "DDR4_DQ6", "DDR4_DQ7"]
+    # at least one reference net must be inclulded. Reference nets are included in the design but clipped.
+    reference_nets = ["GND"]
+    # defining the expansion factor. The value gives the distance for evaluating the cutout extent. Here we define a cutout
+    expansion = 0.01  # 1cm in this case
+    # processing cutout
+    edbapp.cutout(signal_list=signal_nets, reference_list=reference_nets, expansion_size=expansion)
+    # save and close project
+    edbapp.save_edb()
+    edbapp.close_edb()
+    # opening resulting in AEDT to visualize the resulting project.
+    hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version)
+    # After opening AEDT with PyAEDT, if you want to be able to close manually the project you have to release
+    # AEDT from PyAEDT.
+    hfss.release_desktop(close_desktop=False, close_projects=False)
+
+. image:: ../Resources/clipped_layout.png
+  :width: 800
+  :alt: Layout clipping
diff --git a/doc/source/User_guide/edb_queries.rst b/doc/source/User_guide/edb_queries.rst
@@ -1,18 +1,34 @@
 EDB Queries
 ===========
 PyEBD allows layout information queries, this section describe some basic examples:
 
-- stackup layers
+- Load EDB
 .. code:: python
+   # loading EDB
+   edbapp = Edb(edbpath=targetfile, edbversion=desktop_version)
 
-- changing layer thickness
+- Getting layout statistics
 .. code:: python
+   stats = edbapp.get_statistics()
 
 - Nets
 .. code:: python
+   # net list
+   nets.netlist
+   # power nets
+   nets.power
+   # Plotting layout in matplotlib
+   edbapp.nets.plot(None)
+. image:: ../Resources/layout_plot_all_nets.png
+   :width: 800
+   :alt: Plot all nets
 
 - Components
 .. code:: python
+   # Getting all components
+   nets = edbapp.components.instances
+   # Getting pins from components connected to given net
+   u9_gnd_pins = [pin for pin in list(edbapp.components["U9"].pins.values()) if pin.net_name == "GND"]
 
 . image:: ../Resources/aedt_box.png
   :width: 800

diff --git a/doc/source/User_guide/index.rst b/doc/source/User_guide/index.rst
@@ -54,3 +54,8 @@ You can obtain the same result with:
 
    loading_layout
    edb_queries
+   cutout
+   layer_stackup
+   ports
+   simulation_setup
+