FIX: Documentation style typos

ansys · Oct 17, 2024 · ef4f15e · ef4f15e
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diff --git a/doc/source/user_guide/components/create_rlc_component.rst b/doc/source/user_guide/components/create_rlc_component.rst
@@ -37,4 +37,4 @@ This page shows how to create an RLC component between pins:
 
 .. image:: ../../resources/create_rlc_boundary_on_pin.png
   :width: 800
-  :alt: Create rlc boundary
+  :alt: Create RLC boundary
diff --git a/doc/source/user_guide/edb_information_queries/edb_queries.rst b/doc/source/user_guide/edb_information_queries/edb_queries.rst
@@ -8,7 +8,7 @@ these tasks:
 
 - Load a layout.
 - Get statistics.
-- Get nets and plot them in Matplotlib.
+- Get nets and plot them in matplotlib.
 - Get all components and then get pins from components connected to a given net.
 
 .. autosummary::