test #44 done

src/pyedb/grpc/edb_core/components.py

@@ -953,11 +953,11 @@ def replace_rlc_by_gap_boundaries(self, component=None):
             if not component:
                 self._logger.error("component %s not found.", component)
                 return False
-        if component.type in ["OTHER", "IC", "IO"]:
-            self._logger.info("Component %s passed to deactivate is not an RLC.", component.refdes)
+        if component.type in ["other", "ic", "io"]:
+            self._logger.info(f"Component {component.refdes} skipped to deactivate is not an RLC.")
             return False
         component.is_enabled = False
-        return self.add_rlc_boundary(component.refdes, False)
+        return self._pedb.source_excitation.add_rlc_boundary(component.refdes, False)
 
     def deactivate_rlc_component(self, component=None, create_circuit_port=False, pec_boundary=False):
         """Deactivate RLC component with a possibility to convert it to a circuit port.
@@ -1067,7 +1067,7 @@ def add_rlc_boundary(self, component=None, circuit_type=True):
             "`pyedb.grpc.core.excitations.add_rlc_boundary` instead.",
             DeprecationWarning,
         )
-        self._pedb.excitations.add_rlc_boundary(self, component=component, circuit_type=circuit_type)
+        return self._pedb.source_excitation.add_rlc_boundary(self, component=component, circuit_type=circuit_type)
 
     def _create_pin_group_terminal(self, pingroup, isref=False, term_name=None, term_type="circuit"):
         """Creates an EDB pin group terminal from a given EDB pin group.

src/pyedb/grpc/edb_core/source_excitations.py

@@ -665,26 +665,26 @@ def add_rlc_boundary(self, component=None, circuit_type=True):
         if not isinstance(component, Component):  # pragma: no cover
             return False
         self._pedb.components.set_component_rlc(component.name)
-        pins = component.pins
+        pins = list(component.pins.values())
         if len(pins) == 2:  # pragma: no cover
             pin_layer = pins[0].get_layer_range()[0]
             pos_pin_term = PadstackInstanceTerminal.create(
-                self._pedb._active_layout,
-                pins[0].net,
-                "{}_{}".format(component.name, pins[0].name),
-                pins[0],
-                pin_layer,
-                False,
+                layout=self._pedb.active_layout,
+                net=pins[0].net,
+                name=f"{component.name}_{pins[0].name}",
+                padstack_instance=pins[0],
+                layer=pin_layer,
+                is_ref=False,
             )
             if not pos_pin_term:  # pragma: no cover
                 return False
             neg_pin_term = PadstackInstanceTerminal.create(
-                self._pedb._active_layout,
-                pins[1].net,
-                "{}_{}_ref".format(component.name, pins[1].name),
-                pins[1],
-                pin_layer,
-                True,
+                layout=self._pedb.active_layout,
+                net=pins[1].net,
+                name="{}_{}_ref".format(component.name, pins[1].name),
+                padstack_instance=pins[1],
+                layer=pin_layer,
+                is_ref=True,
             )
             if not neg_pin_term:  # pragma: no cover
                 return False

tests/grpc/system/test_edb_components.py

@@ -412,17 +412,13 @@ def test_create_port_on_pin(self, edb_examples):
         assert edbapp.components.create_port_on_pins(refdes="U1", pins=["A28"], reference_pins=["A11", "A16"])
         edbapp.close()
 
-    def test_replace_rlc_by_gap_boundaries(self):
+    def test_replace_rlc_by_gap_boundaries(self, edb_examples):
         """Replace RLC component by RLC gap boundaries."""
-        source_path = os.path.join(local_path, "example_models", test_subfolder, "ANSYS-HSD_V1.aedb")
-        target_path = os.path.join(self.local_scratch.path, "ANSYS-HSD_V1_boundaries.aedb")
-        self.local_scratch.copyfolder(source_path, target_path)
-        edbapp = Edb(target_path, edbversion=desktop_version)
+        # Done
+        edbapp = edb_examples.get_si_verse()
         for refdes, cmp in edbapp.components.instances.items():
             edbapp.components.replace_rlc_by_gap_boundaries(refdes)
-        rlc_list = [
-            term for term in list(edbapp.active_layout.Terminals) if str(term.GetBoundaryType()) == "RlcBoundary"
-        ]
+        rlc_list = [term for term in edbapp.active_layout.terminals if term.boundary_type.name == "RLC"]
         assert len(rlc_list) == 944
         edbapp.close()