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import pyaedt | ||
from pyaedt import Edb, Hfss3dLayout | ||
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# Ansys release version | ||
desktop_version = "2023.2" | ||
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#download and copy the layout file from examples | ||
temp_folder = pyaedt.generate_unique_folder_name() | ||
targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) | ||
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# loading EDB | ||
edbapp = Edb(edbpath=targetfile, edbversion=desktop_version) | ||
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simple_hfss_setup = edbapp.create_hfss_setup("MySimpleSetup") | ||
simple_hfss_setup.set_solution_single_frequency(frequency="5GHz", max_num_passes=30, max_delta_s=0.05) | ||
simple_hfss_setup.add_frequency_sweep(name="MySweep", frequency_sweep=[["linear scale", "0GHz", "10GHz", "0.01GHz"]]) | ||
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multi_freq_setup = edbapp.create_hfss_setup("MyMultiFreqSetup") | ||
multi_freq_setup.set_solution_multi_frequencies(frequencies=["5GHz", "7GHz", "10GHz"], max_num_passes=30, max_delta_s=0.02) | ||
multi_freq_setup.add_frequency_sweep(name="MySweep", frequency_sweep=[["linear scale", "0GHz", "20GHz", "0.01GHz"]]) | ||
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broad_band_sweep = edbapp.create_hfss_setup("MyBroadbandSetup") | ||
broad_band_sweep.set_solution_broadband(low_frequency="5GHz", high_frequency="10GHz", max_num_passes=20, max_delta_s=0.01) | ||
broad_band_sweep.add_frequency_sweep(name="MySweep", frequency_sweep=[["linear scale", "0GHz", "20GHz", "0.01GHz"]]) | ||
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# adding frequency sweeps | ||
multi_freq_sweep_setup = edbapp.create_hfss_setup("MyMultiFrequencySweepSetup") | ||
multi_freq_sweep_setup.set_solution_single_frequency(frequency="5GHz", max_num_passes=30, max_delta_s=0.02) | ||
multi_freq_sweep_setup.add_frequency_sweep(frequency_sweep=[["linear count", "0", "1kHz", 1], | ||
["log scale", "1kHz", "0.1GHz", 10], | ||
["linear scale", "0.1GHz", "10GHz", "0.1GHz"], | ||
]) | ||
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# save and close project | ||
edbapp.save_edb() | ||
edbapp.close_edb() | ||
hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version) | ||
hfss.release_desktop(close_desktop=False, close_projects=False) | ||
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33 changes: 33 additions & 0 deletions
33
doc/source/Scripts_resources/SI/advanced_circuit_port_creation.py
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import pyaedt | ||
from pyaedt import Edb, Hfss3dLayout | ||
from pyaedt.generic.constants import SourceType | ||
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# Ansys release version | ||
desktop_version = "2023.2" | ||
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# download and copy the layout file from examples | ||
temp_folder = pyaedt.generate_unique_folder_name() | ||
targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) | ||
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# loading EDB | ||
edbapp = Edb(edbpath=targetfile, edbversion=desktop_version) | ||
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signal_nets = ["DDR4_DQ0", "DDR4_DQ1", "DDR4_DQ2", "DDR4_DQ3", "DDR4_DQ4", "DDR4_DQ5", "DDR4_DQ6", "DDR4_DQ7"] | ||
reference_nets = ["GND"] | ||
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# processing cutout | ||
edbapp.cutout(signal_list=signal_nets, reference_list=reference_nets, expansion_size=0.01) | ||
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# creating ports on specific component pins | ||
component = edbapp.components["U1"] | ||
for net in signal_nets: | ||
pins = [pin for pin in list(component.pins.values()) if pin.net_name == net] | ||
for pin in pins: | ||
ref_pins = pin.get_reference_pins(reference_net="GND", search_radius=5e-3, max_limit=3, component_only=True) | ||
edbapp.components.create_port_on_pins(refdes="U1", pins=pin, reference_pins=ref_pins) | ||
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# save and close project | ||
edbapp.save_edb() | ||
edbapp.close_edb() | ||
hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version) | ||
hfss.release_desktop(close_desktop=False, close_projects=False) |
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import pyaedt | ||
from pyaedt import Edb, Hfss3dLayout | ||
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# Ansys release version | ||
desktop_version = "2023.2" | ||
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#download and copy the layout file from examples | ||
temp_folder = pyaedt.generate_unique_folder_name() | ||
targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) | ||
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# loading EDB | ||
edbapp = Edb(edbpath=targetfile, edbversion=desktop_version) | ||
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# selecting signal nets to evaluate the extent for clipping the layout | ||
signal_nets = ["DDR4_DQ0", "DDR4_DQ1", "DDR4_DQ2", "DDR4_DQ3", "DDR4_DQ4", "DDR4_DQ5", "DDR4_DQ6", "DDR4_DQ7"] | ||
# at least one reference net must be inclulded. Reference nets are included in the design but clipped. | ||
reference_nets = ["GND"] | ||
# defining the expansion factor. The value gives the distance for evaluating the cutout extent. Here we define a cutout | ||
expansion = 0.01 # 1cm in this case | ||
# processing cutout | ||
edbapp.cutout(signal_list=signal_nets, reference_list=reference_nets, expansion_size=expansion) | ||
# save and close project | ||
edbapp.save_edb() | ||
edbapp.close_edb() | ||
# opening resulting in AEDT to visualize the resulting project. | ||
hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version) | ||
# After opening AEDT with PyAEDT, if you want to be able to close manually the project you have to release | ||
# AEDT from PyAEDT. | ||
hfss.release_desktop(close_desktop=False, close_projects=False) |
30 changes: 30 additions & 0 deletions
30
doc/source/Scripts_resources/SI/create_hfss_excitation_ports.py
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import pyaedt | ||
from pyaedt import Edb, Hfss3dLayout | ||
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# Ansys release version | ||
desktop_version = "2023.2" | ||
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#download and copy the layout file from examples | ||
temp_folder = pyaedt.generate_unique_folder_name() | ||
targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) | ||
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# loading EDB | ||
edbapp = Edb(edbpath=targetfile, edbversion=desktop_version) | ||
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signal_nets = ["DDR4_DQ0", "DDR4_DQ1", "DDR4_DQ2", "DDR4_DQ3", "DDR4_DQ4", "DDR4_DQ5", "DDR4_DQ6", "DDR4_DQ7"] | ||
reference_nets = ["GND"] | ||
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# processing cutout | ||
edbapp.cutout(signal_list=signal_nets, reference_list=reference_nets, expansion_size=0.01) | ||
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if not edbapp.components.create_port_on_component(component="U1", net_list=signal_nets, reference_net="GND"): | ||
edbapp.logger.error("Failed to create ports on component U1") | ||
if not edbapp.components.create_port_on_component(component="U15", net_list=signal_nets, reference_net="GND"): | ||
edbapp.logger.error("Failed to create port on component U15") | ||
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# save and close project | ||
edbapp.save_edb() | ||
edbapp.close_edb() | ||
hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version) | ||
hfss.release_desktop(close_desktop=False, close_projects=False) |
38 changes: 38 additions & 0 deletions
38
doc/source/Scripts_resources/SI/create_siwave_excitation_ports.py
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import pyaedt | ||
from pyaedt import Edb, Hfss3dLayout | ||
from pyaedt.generic.constants import SourceType | ||
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# Ansys release version | ||
desktop_version = "2023.2" | ||
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#download and copy the layout file from examples | ||
temp_folder = pyaedt.generate_unique_folder_name() | ||
targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) | ||
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# loading EDB | ||
edbapp = Edb(edbpath=targetfile, edbversion=desktop_version) | ||
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signal_nets = ["DDR4_DQ0", "DDR4_DQ1", "DDR4_DQ2", "DDR4_DQ3", "DDR4_DQ4", "DDR4_DQ5", "DDR4_DQ6", "DDR4_DQ7"] | ||
reference_nets = ["GND"] | ||
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# processing cutout | ||
edbapp.cutout(signal_list=signal_nets, reference_list=reference_nets, expansion_size=0.01) | ||
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if not edbapp.components.create_port_on_component(component="U1", net_list=signal_nets, | ||
reference_net="GND", | ||
port_type=SourceType.CircPort, | ||
): | ||
edbapp.logger.error("Failed to create ports on component U1") | ||
if not edbapp.components.create_port_on_component(component="U15", | ||
net_list=signal_nets, | ||
reference_net="GND", | ||
port_type=SourceType.CircPort, | ||
): | ||
edbapp.logger.error("Failed to create port on component U15") | ||
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# save and close project | ||
edbapp.save_edb() | ||
edbapp.close_edb() | ||
hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version) | ||
hfss.release_desktop(close_desktop=False, close_projects=False) |
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import pyaedt | ||
from pyaedt import Edb, Hfss3dLayout | ||
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# Ansys release version | ||
desktop_version = "2023.2" | ||
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#download and copy the layout file from examples | ||
temp_folder = pyaedt.generate_unique_folder_name() | ||
targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) | ||
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# loading EDB | ||
edbapp = Edb(edbpath=targetfile, edbversion=desktop_version) | ||
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# ploting layer stackup in matplotlib | ||
edbapp.stackup.plot() | ||
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# retrieving signal layers name | ||
signal_layers = list(edbapp.stackup.signal_layers.keys()) | ||
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# selecting top layer | ||
top_layer = edbapp.stackup.signal_layers[signal_layers[0]] | ||
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# Stackup total thickness | ||
layout_stats = edbapp.get_statistics() | ||
layout_stats.stackup_thickness | ||
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# setting all signal layers thickness to 20um | ||
for layer_name, layer in edbapp.stackup.signal_layers.items(): | ||
layer.thickness = "20um" | ||
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edbapp.materials.add_material(name="MyMaterial", permittivity=4.35, dielectric_loss_tangent=2e-4) | ||
edbapp.materials.add_material(name="MyMetal", conductivity=1e7) | ||
for layer in list(edbapp.stackup.dielectric_layers.values()): | ||
layer.material = "MyMaterial" | ||
for layer in list(edbapp.stackup.signal_layers.values()): | ||
layer.material = "MyMetal" | ||
edbapp.materials.add_material(name="SolderMask", permittivity=3.8, dielectric_loss_tangent=1e-3) | ||
edbapp.stackup.add_layer(layer_name="Solder_mask", base_layer="1_Top", thickness="200um", material="SolderMask") | ||
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import pyaedt | ||
from pyaedt import Edb, Hfss3dLayout | ||
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# Ansys release version | ||
desktop_version = "2023.2" | ||
|
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#download and copy the layout file from examples | ||
temp_folder = pyaedt.generate_unique_folder_name() | ||
targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) | ||
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# loading EDB | ||
edbapp = Edb(edbpath=targetfile, edbversion=desktop_version) | ||
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# Some layout statistics | ||
stats = edbapp.get_statistics() | ||
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# When edb is loaded, we can access all layout information | ||
nets = edbapp.nets | ||
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# net list | ||
nets.netlist | ||
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# power nets | ||
nets.power | ||
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# Getting components from specific net | ||
nets.power["GND"].components | ||
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# Getting pins from components | ||
edbapp.components["U9"].pins | ||
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# Getting pins from components connected to given net | ||
u9_gnd_pins = [pin for pin in list(edbapp.components["U9"].pins.values()) if pin.net_name == "GND"] | ||
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# Plotting layout in matplotlib | ||
edbapp.nets.plot(None) | ||
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# plotting specific net | ||
edbapp.nets.plot("GND") |
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================================================== | ||
High frequency channel extraction workflow example | ||
================================================== | ||
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This section describes an automated workflow using PyANSYS-EDB for high frequency channel extraction: | ||
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.. toctree:: | ||
:maxdepth: 2 | ||
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|
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Clipping layout | ||
=============== | ||
Because most of the time only a specific part of a layout must be simulated, clipping the design | ||
needs to be performed to reduce computer resources and speed up simulation. This section describes | ||
how to clip a design based on nets selection. | ||
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.. code:: python | ||
import pyaedt | ||
from pyedb import Edb, Hfss3dLayout | ||
# Ansys release version | ||
desktop_version = "2023.2" | ||
#download and copy the layout file from examples | ||
temp_folder = pyaedt.generate_unique_folder_name() | ||
targetfile = pyaedt.downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) | ||
# loading EDB | ||
edbapp = Edb(edbpath=targetfile, edbversion=desktop_version) | ||
# selecting signal nets to evaluate the extent for clipping the layout | ||
signal_nets = ["DDR4_DQ0", "DDR4_DQ1", "DDR4_DQ2", "DDR4_DQ3", "DDR4_DQ4", "DDR4_DQ5", "DDR4_DQ6", "DDR4_DQ7"] | ||
# at least one reference net must be inclulded. Reference nets are included in the design but clipped. | ||
reference_nets = ["GND"] | ||
# defining the expansion factor. The value gives the distance for evaluating the cutout extent. Here we define a cutout | ||
expansion = 0.01 # 1cm in this case | ||
# processing cutout | ||
edbapp.cutout(signal_list=signal_nets, reference_list=reference_nets, expansion_size=expansion) | ||
# save and close project | ||
edbapp.save_edb() | ||
edbapp.close_edb() | ||
# opening resulting in AEDT to visualize the resulting project. | ||
hfss = Hfss3dLayout(projectname=targetfile, specified_version=desktop_version) | ||
# After opening AEDT with PyAEDT, if you want to be able to close manually the project you have to release | ||
# AEDT from PyAEDT. | ||
hfss.release_desktop(close_desktop=False, close_projects=False) | ||
. image:: ../Resources/clipped_layout.png | ||
:width: 800 | ||
:alt: Layout clipping |
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@@ -54,3 +54,8 @@ You can obtain the same result with: | |
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loading_layout | ||
edb_queries | ||
cutout | ||
layer_stackup | ||
ports | ||
simulation_setup | ||
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