REFACTOR: Design initialization in PyAEDT APP (#5747)

ansys · Feb 7, 2025 · 29b7d2f · 29b7d2f
1 parent 6f36565
commit 29b7d2f
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Showing 4 changed files with 24 additions and 6 deletions.
diff --git a/src/ansys/aedt/core/application/aedt_objects.py b/src/ansys/aedt/core/application/aedt_objects.py
@@ -390,13 +390,18 @@ def oeditor(self):
         ----------
         >>> oEditor = oDesign.SetActiveEditor("SchematicEditor")"""
         if not self._oeditor and self._odesign:
-            if self.design_type in ["Circuit Design", "Twin Builder", "Maxwell Circuit", "EMIT"]:
+            if self.design_type in ["Circuit Design"]:
+                self._oeditor = self._odesign.GetEditor("SchematicEditor")
+                if is_linux and settings.aedt_version == "2024.1":  # pragma: no cover
+                    time.sleep(1)
+                    self.desktop_class.close_windows()
+            elif self.design_type in ["Twin Builder", "Maxwell Circuit", "EMIT"]:
                 self._oeditor = self._odesign.SetActiveEditor("SchematicEditor")
                 if is_linux and settings.aedt_version == "2024.1":  # pragma: no cover
                     time.sleep(1)
                     self.desktop_class.close_windows()
             elif self.design_type in ["HFSS 3D Layout Design", "HFSS3DLayout"]:
-                self._oeditor = self._odesign.SetActiveEditor("Layout")
+                self._oeditor = self._odesign.GetEditor("Layout")
             elif self.design_type in ["RMxprt", "RMxprtSolution"]:
                 self._oeditor = self._odesign.SetActiveEditor("Machine")
             elif self.design_type in ["Circuit Netlist"]:

diff --git a/src/ansys/aedt/core/application/design.py b/src/ansys/aedt/core/application/design.py
@@ -1124,11 +1124,19 @@ def _find_design(self) -> Tuple[str, str]:
                         valids.append(name)
                     elif self._temp_solution_type in des.GetSolutionType():
                         valids.append(name)
-            if len(valids) != 1:
-                warning_msg = "No consistent unique design is present. Inserting a new design."
-            else:
+            if len(valids) > 1:
+                des_name = self.oproject.GetActiveDesign().GetName()
+                if des_name in valids:
+                    activedes = self.oproject.GetActiveDesign().GetName()
+                else:
+                    activedes = valids[0]
+                warning_msg = f"Active Design set to {valids[0]}"
+            elif len(valids) == 1:
                 activedes = valids[0]
                 warning_msg = f"Active Design set to {valids[0]}"
+            else:
+                warning_msg = "No consistent unique design is present. Inserting a new design."
+
         # legacy support for version < 2021.2
         elif self.design_list:  # pragma: no cover
             self._odesign = self._oproject.GetDesign(self.design_list[0])
@@ -4091,6 +4099,7 @@ def _assert_consistent_design_type(self, des_name):
                     raise ValueError(f"Specified design is not of type {self._design_type}.")
             elif self._design_type not in {"RMxprtSolution", "ModelCreation"}:
                 raise ValueError(f"Specified design is not of type {self._design_type}.")
+
             return True
         elif ":" in des_name:
             try:

diff --git a/src/ansys/aedt/core/desktop.py b/src/ansys/aedt/core/desktop.py
@@ -774,6 +774,8 @@ def active_design(self, project_object=None, name=None, design_type=None):
         if is_linux and settings.aedt_version == "2024.1" and design_type == "Circuit Design":  # pragma: no cover
             time.sleep(1)
             self.close_windows()
+        warning_msg = f"Active Design set to {active_design.GetName()}"
+        settings.logger.info(warning_msg)
         return active_design
 
     @pyaedt_function_handler()

diff --git a/tests/system/general/test_20_HFSS.py b/tests/system/general/test_20_HFSS.py
@@ -1570,7 +1570,9 @@ def test_63_set_phase_center_per_port(self):
         ),
     )
     def test_64_import_dxf(self, dxf_file: str, object_count: int, self_stitch_tolerance: float):
-        design_name = self.aedtapp.insert_design("test_64_import_dxf")
+        from pyedb.generic.general_methods import generate_unique_name
+
+        design_name = self.aedtapp.insert_design(generate_unique_name("test_64_import_dxf"))
         self.aedtapp.set_active_design(design_name)
         dxf_layers = self.aedtapp.get_dxf_layers(dxf_file)
         assert isinstance(dxf_layers, list)