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* | ||
!Vocab | ||
!Vocab/** | ||
!.gitignore | ||
!config | ||
!config/vocabularies | ||
!config/vocabularies/ANSYS | ||
!config/vocabularies/ANSYS/** | ||
!.gitignore |
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# # DC IR analysis | ||
# This example shows how to configure EDB for DC IR analysis and load EDB into the HFSS 3D Layout UI for analysis and | ||
# postprocessing. | ||
# | ||
# - Set up EDB: | ||
# | ||
# - Edit via padstack. | ||
# - Assign SPICE model to components. | ||
# - Create pin groups. | ||
# - Create voltage and current sources. | ||
# - Create SIwave DC analysis. | ||
# - Create cutout. | ||
# | ||
# - Import EDB into HFSS 3D Layout: | ||
# | ||
# - Analyze. | ||
# - Get DC IR analysis results. | ||
# | ||
# Keywords: **HFSS 3D Layout**, **DC IR**. | ||
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# ## Perform imports and define constants | ||
# Perform required imports. | ||
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import json | ||
import os | ||
import tempfile | ||
import time | ||
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import ansys.aedt.core | ||
from ansys.aedt.core.downloads import download_file | ||
from pyedb import Edb | ||
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# Define constants. | ||
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AEDT_VERSION = "2024.2" | ||
NUM_CORES = 4 | ||
NG_MODE = False # Open AEDT UI when it is launched. | ||
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# Download example board. | ||
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temp_folder = tempfile.TemporaryDirectory(suffix=".ansys") | ||
aedb = download_file(source="edb/ANSYS-HSD_V1.aedb", destination=temp_folder.name) | ||
download_file( | ||
source="spice", name="ferrite_bead_BLM15BX750SZ1.mod", destination=temp_folder.name | ||
) | ||
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# ## Create configuration file | ||
# This example uses a configuration file to set up the layout for analysis. | ||
# Initialize and create an empty dictionary to host all configurations. | ||
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cfg = dict() | ||
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# Define model library paths. | ||
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cfg["general"] = { | ||
"s_parameter_library": os.path.join(temp_folder.name, "touchstone"), | ||
"spice_model_library": os.path.join(temp_folder.name, "spice"), | ||
} | ||
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# ### Change via hole size and plating thickness | ||
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cfg["padstacks"] = { | ||
"definitions": [ | ||
{"name": "v40h15-3", "hole_diameter": "0.2mm", "hole_plating_thickness": "25um"} | ||
], | ||
} | ||
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# ### Assign SPICE models | ||
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cfg["spice_models"] = [ | ||
{ | ||
"name": "ferrite_bead_BLM15BX750SZ1", # Give a name to the SPICE Mode. | ||
"component_definition": "COIL-1008CS_V", # Part name of the components | ||
"file_path": "ferrite_bead_BLM15BX750SZ1.mod", # File name or full file path to the SPICE file. | ||
"sub_circuit_name": "BLM15BX750SZ1", | ||
"apply_to_all": True, # If True, SPICE model is to be assigned to all components share the same part name. | ||
# If False, only assign SPICE model to components in "components". | ||
"components": [], | ||
} | ||
] | ||
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# ### Create voltage source | ||
# Create a voltage source from a net. | ||
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cfg["sources"] = [ | ||
{ | ||
"name": "VSOURCE_5V", | ||
"reference_designator": "U4", | ||
"type": "voltage", | ||
"magnitude": 5, | ||
"positive_terminal": {"net": "5V"}, | ||
"negative_terminal": {"net": "GND"}, | ||
} | ||
] | ||
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# ### Create current sources | ||
# Create current sources between the net and pin group. | ||
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cfg["pin_groups"] = [{"name": "J5_GND", "reference_designator": "J5", "net": "GND"}] | ||
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cfg["sources"].append( | ||
{ | ||
"name": "J5_VCCR", | ||
"reference_designator": "J5", | ||
"type": "current", | ||
"magnitude": 0.5, | ||
"positive_terminal": {"net": "SFPA_VCCR"}, | ||
"negative_terminal": { | ||
"pin_group": "J5_GND" # Defined in "pin_groups" section. | ||
}, | ||
} | ||
) | ||
cfg["sources"].append( | ||
{ | ||
"name": "J5_VCCT", | ||
"reference_designator": "J5", | ||
"type": "current", | ||
"magnitude": 0.5, | ||
"positive_terminal": {"net": "SFPA_VCCT"}, | ||
"negative_terminal": { | ||
"pin_group": "J5_GND" # Defined in "pin_groups" section. | ||
}, | ||
} | ||
) | ||
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# ### Create SIwave DC analysis | ||
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cfg["setups"] = [{"name": "siwave_dc", "type": "siwave_dc", "dc_slider_position": 0}] | ||
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# ### Define cutout | ||
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cfg["operations"] = { | ||
"cutout": { | ||
"signal_list": ["SFPA_VCCR", "SFPA_VCCT", "5V"], | ||
"reference_list": ["GND"], | ||
"extent_type": "ConvexHull", | ||
"expansion_size": 0.002, | ||
"use_round_corner": False, | ||
"output_aedb_path": "", | ||
"open_cutout_at_end": True, | ||
"use_pyaedt_cutout": True, | ||
"number_of_threads": 4, | ||
"use_pyaedt_extent_computing": True, | ||
"extent_defeature": 0, | ||
"remove_single_pin_components": False, | ||
"custom_extent": "", | ||
"custom_extent_units": "mm", | ||
"include_partial_instances": False, | ||
"keep_voids": True, | ||
"check_terminals": False, | ||
"include_pingroups": False, | ||
"expansion_factor": 0, | ||
"maximum_iterations": 10, | ||
"preserve_components_with_model": False, | ||
"simple_pad_check": True, | ||
"keep_lines_as_path": False, | ||
} | ||
} | ||
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# ### Save configuration as a JSON file | ||
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pi_json = os.path.join(temp_folder.name, "pi.json") | ||
with open(pi_json, "w") as f: | ||
json.dump(cfg, f, indent=4, ensure_ascii=False) | ||
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# ## Load configuration into EDB | ||
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# Load the configuration from the JSON file into EDB. | ||
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edbapp = Edb(aedb, edbversion=AEDT_VERSION) | ||
edbapp.configuration.load(config_file=pi_json) | ||
edbapp.configuration.run() | ||
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# # Load configuration into EDB | ||
edbapp.nets.plot(None, None, color_by_net=True) | ||
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# ## Save and close EDB | ||
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edbapp.save() | ||
edbapp.close() | ||
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# The configured EDB file is saved in the temporary folder. | ||
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print(temp_folder.name) | ||
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# ## Analyze DCIR with SIwave | ||
# | ||
# The HFSS 3D Layout interface to SIwave is used to open the EDB and run the DCIR analysis | ||
# using SIwave | ||
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# ### Load EDB into HFSS 3D Layout. | ||
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siw = ansys.aedt.core.Hfss3dLayout( | ||
aedb, version=AEDT_VERSION, non_graphical=NG_MODE, new_desktop=True | ||
) | ||
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# ### Analyze | ||
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siw.analyze(cores=NUM_CORES) | ||
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# ### Get DC IR results | ||
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siw.get_dcir_element_data_current_source("siwave_dc") | ||
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# ## Release AEDT | ||
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siw.save_project() | ||
siw.release_desktop() | ||
# Wait 3 seconds to allow AEDT to shut down before cleaning the temporary directory. | ||
time.sleep(3) | ||
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# ## Clean up | ||
# | ||
# All project files are saved in the folder ``temp_folder.name``. | ||
# If you've run this example as a Jupyter notebook, you | ||
# can retrieve those project files. The following cell | ||
# removes all temporary files, including the project folder. | ||
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temp_folder.cleanup() |
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