Fix typo in amd64 gs_seg register name (#192)

angr · Dec 14, 2023 · c1538e5 · c1538e5
1 parent 37c3815
commit c1538e5
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/archinfo/arch_amd64.py b/archinfo/arch_amd64.py
@@ -443,7 +443,7 @@ def _configure_keystone(self):
         Register(name="ds_seg", size=2, vex_name="ds"),
         Register(name="es_seg", size=2, vex_name="es"),
         Register(name="fs_seg", size=2, vex_name="fs"),
-        Register(name="fs_seg", size=2, vex_name="gs"),
+        Register(name="gs_seg", size=2, vex_name="gs"),
         Register(name="ss_seg", size=2, vex_name="ss"),
     ]