RTL Co-Simulation #21

geotrieu · 2023-11-22T03:18:28Z

Summary of Changes:

RTL MVM module compatible with the new mlp_int8 example
Changed mlp_int8 example to support co-simulation of MVM modules (native SysC/Verilated RTL)
Changed gen_testcase.py to support this new format when generating layer_mvm_config
Added numerous timing mechanisms to the add, rtl_add designs
Patched Verilator Warnings bug stemming from "-Wextra and -pedantic" by explicitly specifying Verilator is a SYSTEM library
Patched several memory leaks from the rtl_add design
Updated generate_port_mappings and generate_wrapper scripts to support multiple AXI-S ports
Updated tests to cover new cases for aforementioned scripts
Patched several bugs with the Verilog parser library related to erroneously parsing inputs and outputs in comments
Added failsafe check in RAD-Sim to ensure a module is instantiated if routed on the NoC (prevents seg fault)
Added CI Test for testing Verilator (mlp_int8 example)

…example, added module instantiation check to RAD-SIM

…lated modules

… dev-gtrieu

andrewboutros · 2023-11-29T20:57:32Z

rad-sim/example-designs/add/add_driver.cpp

@@ -31,6 +31,8 @@ void add_driver::source() {
  client_valid.write(false);
  wait();
  rst.write(false);
+  start_cycle = GetSimulationCycle(1.0);


Is there a reason why the clock period is hardcoded to 1ns here?
I think it should be set to the driver clock period from the config.yml file

Good catch, I replaced it all with the "sim_driver_period" parameter

rad-sim/example-designs/add/add_driver.cpp

rad-sim/example-designs/mlp_int8/mlp_driver.cpp

andrewboutros · 2023-11-29T21:06:44Z

rad-sim/example-designs/mlp_int8/mlp_int8_system.cpp

-  std::vector<unsigned int> num_mvms;
+  unsigned int num_layers;
+  std::string num_mvms_layer, num_mvms_rtl_layer;
+  std::string layer_mvms;
  line_stream >> num_layers;
  num_mvms.resize(num_layers);


Should we change this variable name (and other related ones) to explicitly mention it is for SystemC MVMs (e.g. num_mvms_systemc)

I think this also might apply to other files that have similar configuration parsing code (e.g. mlp_driver)

Great suggestion, I renamed all the ambiguous names to specify sysc, and also renamed the system c MVM module to sysc_mvm so its more clear

rad-sim/example-designs/rtl_add/rtl_add_driver.cpp

andrewboutros · 2023-11-29T21:18:38Z

rad-sim/scripts/generate_port_mappings.py

@@ -5,7 +5,9 @@
 from pathlib import Path


I think this is a critical file that I can see people needing to change later for different reasons, but it is very lightly commented. Could you add high-level comments at the top of the file and then detailed comments on different sections to explain what is going on in it.

I added some comments describing functionality at the top, and also some comments at each function block.

andrewboutros · 2023-11-29T21:19:57Z

rad-sim/scripts/generate_wrapper.py

@@ -6,22 +6,27 @@
 import argparse


This one is also lightly commented. I think this is a critical script that should be heavily commented for future modifications/extensions.

I added some comments describing the functionality. Most code in this file is actually either in plain English (value assertions with messages), or simply lines of code writing C++ code. I tried not to put too many comments there since it doesnt help that much

andrewboutros · 2023-11-29T21:20:47Z

rad-sim/scripts/verilog_parser.py

@@ -8,6 +8,9 @@



Maybe a high-level comment at the top of this file to explain why it is needed and when it is used.

geotrieu added 5 commits November 16, 2023 17:44

Updated port mapping and wrapper generation scripts, updated RTL_Add …

75e1ea8

…example, added module instantiation check to RAD-SIM

MLP Co-Simulated Design with both native SystemC modules and RTL veri…

12f3fb3

…lated modules

Resolved Verilator Warnings

9d87842

Fixed erroneous requirement of Verilator for RAD-Sim

f75d3e9

Added CI Test for Co-Simulation

5b12363

geotrieu requested a review from andrewboutros November 22, 2023 05:39

geotrieu added 3 commits November 23, 2023 14:50

Merge branch 'main' of https://github.com/andrewboutros/rad-flow into…

11adb2a

… dev-gtrieu

Added built-in cleanup call for verilated modules

b8d180f

Generated MVM file after built-in clean up change

b625f85

geotrieu mentioned this pull request Nov 28, 2023

RAD-Sim Design Correctness Reporting #22

Merged

geotrieu added 3 commits November 29, 2023 13:27

Updated adder example to use new AXI-S format

df12a77

Eliminated requirement to enter AXI-S width for non AXI-S modules

e74b3fc

RTL Code Documentation CMakeLists improvement

03680c2

andrewboutros reviewed Nov 29, 2023

View reviewed changes

Added comments and renamed some variables to make code appear cleaner

df50a77

andrewboutros approved these changes Dec 1, 2023

View reviewed changes

andrewboutros merged commit fd857b9 into main Dec 1, 2023
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RTL Co-Simulation #21

RTL Co-Simulation #21

geotrieu commented Nov 22, 2023 •

edited

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andrewboutros Nov 29, 2023

geotrieu Nov 30, 2023

andrewboutros Nov 29, 2023

andrewboutros Nov 29, 2023

geotrieu Nov 30, 2023

andrewboutros Nov 29, 2023

geotrieu Nov 30, 2023

andrewboutros Nov 29, 2023

geotrieu Nov 30, 2023

andrewboutros Nov 29, 2023

geotrieu Nov 30, 2023

RTL Co-Simulation #21

RTL Co-Simulation #21

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geotrieu commented Nov 22, 2023 • edited Loading

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geotrieu commented Nov 22, 2023 •

edited

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