Skip to content

Commit

Permalink
TO-BE-TESTED: Ported mlp_int8 design to multi-rad code
Browse files Browse the repository at this point in the history
  • Loading branch information
abnashkb committed Jul 30, 2024
1 parent f603782 commit ce1670b
Show file tree
Hide file tree
Showing 29 changed files with 151 additions and 113 deletions.
3 changes: 3 additions & 0 deletions rad-sim/example-designs/mlp/compiler/gen_testcase.py
Original file line number Diff line number Diff line change
Expand Up @@ -206,7 +206,10 @@
placement_file.write('output_collector 0 ' + str(router_ids[idx]) + ' axis\n')
idx = idx + 1
clocks_file.write('output_collector 0 0\n')

placement_file.write('portal_inst 0 16 axis\n')
clocks_file.write('portal_inst 0 0\n')

placement_file.close()
clocks_file.close()

Expand Down
1 change: 1 addition & 0 deletions rad-sim/example-designs/mlp/mlp.clks
Original file line number Diff line number Diff line change
Expand Up @@ -14,3 +14,4 @@ input_dispatcher1 0 0
input_dispatcher2 0 0
input_dispatcher3 0 0
output_collector 0 0
portal_inst 0 0
28 changes: 14 additions & 14 deletions rad-sim/example-designs/mlp/mlp.place
Original file line number Diff line number Diff line change
@@ -1,17 +1,17 @@
layer0_mvm0 0 2 axis
layer0_mvm1 0 15 axis
layer0_mvm2 0 9 axis
layer0_mvm3 0 1 axis
layer1_mvm0 0 7 axis
layer1_mvm1 0 10 axis
layer1_mvm2 0 8 axis
layer0_mvm0 0 3 axis
layer0_mvm1 0 9 axis
layer0_mvm2 0 0 axis
layer0_mvm3 0 12 axis
layer1_mvm0 0 14 axis
layer1_mvm1 0 8 axis
layer1_mvm2 0 5 axis
layer2_mvm0 0 6 axis
layer2_mvm1 0 5 axis
layer2_mvm1 0 4 axis
layer3_mvm0 0 11 axis
layer3_mvm1 0 0 axis
input_dispatcher0 0 4 axis
input_dispatcher1 0 13 axis
input_dispatcher2 0 3 axis
input_dispatcher3 0 14 axis
output_collector 0 12 axis
layer3_mvm1 0 7 axis
input_dispatcher0 0 2 axis
input_dispatcher1 0 1 axis
input_dispatcher2 0 10 axis
input_dispatcher3 0 13 axis
output_collector 0 15 axis
portal_inst 0 16 axis
4 changes: 2 additions & 2 deletions rad-sim/example-designs/mlp_int8/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -54,5 +54,5 @@ set(hdrfiles

add_compile_options(-Wall -Wextra -pedantic)

add_library(design STATIC ${srcfiles} ${hdrfiles})
target_link_libraries(design PUBLIC SystemC::systemc booksim noc rtl_designs)
add_library(mlp_int8 STATIC ${srcfiles} ${hdrfiles})
target_link_libraries(mlp_int8 PUBLIC SystemC::systemc booksim noc rtl_designs)
3 changes: 3 additions & 0 deletions rad-sim/example-designs/mlp_int8/compiler/gen_testcase.py
Original file line number Diff line number Diff line change
Expand Up @@ -76,6 +76,9 @@
idx = idx + 1
clocks_file.write('inst_loader 0 0\n')

placement_file.write('portal_inst 0 16 axis\n')
clocks_file.write('portal_inst 0 0\n')

placement_file.close()
clocks_file.close()

Expand Down
20 changes: 12 additions & 8 deletions rad-sim/example-designs/mlp_int8/config.yml
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ noc:
clk_period: [1.0]
payload_width: [166]
topology: ['mesh']
dim_x: [4]
dim_x: [5]
dim_y: [4]
routing_func: ['dim_order']
vcs: [5]
Expand All @@ -27,11 +27,15 @@ noc_adapters:
out_arbiter: ['priority_rr']
vc_mapping: ['direct']

design:
name: 'mlp_int8'
noc_placement: ['mlp.place']
clk_periods: [5.0]
config rad1:
design:
name: 'mlp_int8'
noc_placement: ['mlp.place']
clk_periods: [5.0]

telemetry:
log_verbosity: 2
traces: []
cluster:
sim_driver_period: 5.0
telemetry_log_verbosity: 2
telemetry_traces: []
num_rads: 1
cluster_configs: ['rad1']
1 change: 1 addition & 0 deletions rad-sim/example-designs/mlp_int8/mlp.clks
Original file line number Diff line number Diff line change
Expand Up @@ -14,3 +14,4 @@ input_dispatcher2 0 0
output_collector 0 0
weight_loader 0 0
inst_loader 0 0
portal_inst 0 0
31 changes: 16 additions & 15 deletions rad-sim/example-designs/mlp_int8/mlp.place
Original file line number Diff line number Diff line change
@@ -1,16 +1,17 @@
layer0_mvm0 0 3 axis
layer0_mvm1 0 1 axis
layer0_mvm2 0 0 axis
layer1_mvm0 0 2 axis
layer1_mvm1 0 5 axis
layer1_mvm2 0 6 axis
layer2_mvm0 0 9 axis
layer2_mvm1 0 11 axis
layer3_mvm0 0 14 axis
layer3_mvm1 0 10 axis
input_dispatcher0 0 13 axis
input_dispatcher1 0 4 axis
input_dispatcher2 0 12 axis
output_collector 0 7 axis
weight_loader 0 8 axis
layer0_mvm0 0 10 axis
layer0_mvm1 0 2 axis
layer0_mvm2 0 11 axis
layer1_mvm0 0 14 axis
layer1_mvm1 0 13 axis
layer1_mvm2 0 12 axis
layer2_mvm0 0 3 axis
layer2_mvm1 0 5 axis
layer3_mvm0 0 9 axis
layer3_mvm1 0 0 axis
input_dispatcher0 0 4 axis
input_dispatcher1 0 8 axis
input_dispatcher2 0 7 axis
output_collector 0 1 axis
weight_loader 0 6 axis
inst_loader 0 15 axis
portal_inst 0 16 axis
29 changes: 16 additions & 13 deletions rad-sim/example-designs/mlp_int8/mlp_driver.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3,9 +3,9 @@
bool ParseWeights(std::vector<std::vector<int>>& weights,
std::vector<unsigned int>& rf_ids, std::vector<unsigned int>& rf_addrs,
std::vector<unsigned int>& layer_ids, std::vector<unsigned int>& mvm_ids,
unsigned int num_layers, std::vector<unsigned int>& num_mvms) {
unsigned int num_layers, std::vector<unsigned int>& num_mvms, unsigned int _rad_id) {

std::string design_root_dir = radsim_config.GetStringKnob("radsim_user_design_root_dir");
std::string design_root_dir = radsim_config.GetStringKnobShared("radsim_user_design_root_dir", _rad_id);
for (unsigned int l = 0; l < num_layers; l++) {
for (unsigned int m = 0; m < num_mvms[l]; m++) {
for (unsigned int d = 0; d < DPES; d++) {
Expand Down Expand Up @@ -43,8 +43,8 @@ bool ParseWeights(std::vector<std::vector<int>>& weights,
bool ParseInstructions(std::vector<mvm_inst> &insts,
std::vector<unsigned int>& layer_ids,
std::vector<unsigned int>& mvm_ids,
unsigned int num_layers, std::vector<unsigned int>& num_mvms) {
std::string design_root_dir = radsim_config.GetStringKnob("radsim_user_design_root_dir");
unsigned int num_layers, std::vector<unsigned int>& num_mvms, unsigned int _rad_id) {
std::string design_root_dir = radsim_config.GetStringKnob("radsim_user_design_root_dir", _rad_id);

for (unsigned int l = 0; l < num_layers; l++) {
for (unsigned int m = 0; m < num_mvms[l]; m++) {
Expand Down Expand Up @@ -106,12 +106,13 @@ bool ParseIO(std::vector<std::vector<int>>& data_vec, std::string& io_filename)
return true;
}

mlp_driver::mlp_driver(const sc_module_name& name) : sc_module(name) {
mlp_driver::mlp_driver(const sc_module_name& name, RADSimDesignContext* radsim_design_) : sc_module(name) {
this->radsim_design = radsim_design_;
start_cycle = 0;
end_cycle = 0;

// Parse design configuration (number of layers & number of MVM per layer)
std::string design_root_dir = radsim_config.GetStringKnob("radsim_user_design_root_dir");
std::string design_root_dir = radsim_config.GetStringKnobPerRad("radsim_user_design_root_dir", radsim_design->rad_id);
std::string design_config_filename = design_root_dir + "/compiler/layer_mvm_config";
std::ifstream design_config_file(design_config_filename);
if (!design_config_file) {
Expand Down Expand Up @@ -144,11 +145,11 @@ mlp_driver::mlp_driver(const sc_module_name& name) : sc_module(name) {

// Parse weights
ParseWeights(weight_data, weight_rf_id, weight_rf_addr, weight_layer_id,
weight_mvm_id, num_layers, num_mvms_total);
weight_mvm_id, num_layers, num_mvms_total, radsim_design->rad_id);
std::cout << "# Weight vectors = " << weight_data.size() << std::endl;

// Parse instructions
ParseInstructions(inst_data, inst_layer_id, inst_mvm_id, num_layers, num_mvms_total);
ParseInstructions(inst_data, inst_layer_id, inst_mvm_id, num_layers, num_mvms_total, radsim_design->rad_id);
std::cout << "# Instructions = " << inst_data.size() << std::endl;

// Parse test inputs
Expand Down Expand Up @@ -258,7 +259,7 @@ void mlp_driver::source() {
wait();
}

start_cycle = GetSimulationCycle(radsim_config.GetDoubleKnob("sim_driver_period"));
start_cycle = GetSimulationCycle(radsim_config.GetDoubleKnobShared("sim_driver_period"));
start_time = std::chrono::steady_clock::now();
wait();

Expand Down Expand Up @@ -309,23 +310,25 @@ void mlp_driver::sink() {
}
if (mistake) {
std::cout << "FAILURE - Some outputs NOT matching!" << std::endl;
radsim_design.ReportDesignFailure();
radsim_design->ReportDesignFailure();
} else {
std::cout << "SUCCESS - All outputs are matching!" << std::endl;
}

end_cycle = GetSimulationCycle(radsim_config.GetDoubleKnob("sim_driver_period"));
end_cycle = GetSimulationCycle(radsim_config.GetDoubleKnobShared("sim_driver_period"));
end_time = std::chrono::steady_clock::now();
std::cout << "Simulation Cycles = " << end_cycle - start_cycle << std::endl;
std::cout << "Simulation Time = " << std::chrono::duration_cast<std::chrono::milliseconds> (end_time - start_time).count() << " ms" << std::endl;
NoCTransactionTelemetry::DumpStatsToFile("stats.csv");
NoCFlitTelemetry::DumpNoCFlitTracesToFile("flit_traces.csv");

std::vector<double> aggregate_bandwidths = NoCTransactionTelemetry::DumpTrafficFlows("traffic_flows",
end_cycle - start_cycle, radsim_design.GetNodeModuleNames());
end_cycle - start_cycle, radsim_design.GetNodeModuleNames(), radsim_design->rad_id);
std::cout << "Aggregate NoC BW = " << aggregate_bandwidths[0] / 1000000000 << " Gbps" << std::endl;

sc_stop();
//sc_stop();
this->radsim_design->set_rad_done(); //flag to replace sc_stop calls
return;
}

void mlp_driver::assign() {
Expand Down
4 changes: 3 additions & 1 deletion rad-sim/example-designs/mlp_int8/mlp_driver.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,9 @@ class mlp_driver : public sc_module {
sc_out<bool> collector_fifo_ren;
sc_in<data_vector<sc_int<IPRECISION>>> collector_fifo_rdata;

mlp_driver(const sc_module_name& name);
RADSimDesignContext* radsim_design;

mlp_driver(const sc_module_name& name, RADSimDesignContext* radsim_design_);
~mlp_driver();

void source();
Expand Down
11 changes: 7 additions & 4 deletions rad-sim/example-designs/mlp_int8/mlp_int8_system.cpp
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
#include "mlp_int8_system.hpp"

mlp_int8_system::mlp_int8_system(const sc_module_name& name, sc_clock* driver_clk_sig) :
mlp_int8_system::mlp_int8_system(const sc_module_name& name, sc_clock* driver_clk_sig, RADSimDesignContext* radsim_design) :
sc_module(name) {

// Parse design configuration (number of layers and number of MVMs per layer)
std::string design_root_dir = radsim_config.GetStringKnob("radsim_user_design_root_dir");
std::string design_root_dir = radsim_config.GetStringKnobPerRad("radsim_user_design_root_dir", radsim_design->rad_id);
std::string design_config_filename = design_root_dir + "/compiler/layer_mvm_config";
std::ifstream design_config_file(design_config_filename);
if (!design_config_file) {
Expand Down Expand Up @@ -37,7 +37,7 @@ mlp_int8_system::mlp_int8_system(const sc_module_name& name, sc_clock* driver_cl
init_vector<sc_signal<data_vector<sc_int<IPRECISION>>>>::init_sc_vector(dispatcher_fifo_wdata_signal, num_mvms_total[0]);

// Instantiate driver
mlp_driver_inst = new mlp_driver("mlp_driver");
mlp_driver_inst = new mlp_driver("mlp_driver", radsim_design);
mlp_driver_inst->clk(*driver_clk_sig);
mlp_driver_inst->rst(rst_sig);
mlp_driver_inst->weight_loader_weight_fifo_rdy(weight_loader_weight_fifo_rdy_signal);
Expand Down Expand Up @@ -72,7 +72,7 @@ mlp_int8_system::mlp_int8_system(const sc_module_name& name, sc_clock* driver_cl
mlp_driver_inst->collector_fifo_rdata(collector_fifo_rdata_signal);

// Instantiate design top-level
mlp_inst = new mlp_top("mlp_top");
mlp_inst = new mlp_top("mlp_top", radsim_design);
mlp_inst->rst(rst_sig);
mlp_inst->weight_loader_weight_fifo_rdy(weight_loader_weight_fifo_rdy_signal);
mlp_inst->weight_loader_weight_fifo_wen(weight_loader_weight_fifo_wen_signal);
Expand Down Expand Up @@ -104,6 +104,9 @@ mlp_int8_system::mlp_int8_system(const sc_module_name& name, sc_clock* driver_cl
mlp_inst->collector_fifo_rdy(collector_fifo_rdy_signal);
mlp_inst->collector_fifo_ren(collector_fifo_ren_signal);
mlp_inst->collector_fifo_rdata(collector_fifo_rdata_signal);

//add _top as dut instance for parent class design_system
this->design_dut_inst = mlp_inst;
}

mlp_int8_system::~mlp_int8_system() {
Expand Down
5 changes: 3 additions & 2 deletions rad-sim/example-designs/mlp_int8/mlp_int8_system.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,9 @@
#include <mlp_top.hpp>
#include <sim_utils.hpp>
#include <vector>
#include <design_system.hpp>

class mlp_int8_system : public sc_module {
class mlp_int8_system : public design_system {
private:
std::vector<unsigned int> num_mvms_sysc;
std::vector<unsigned int> num_mvms_rtl;
Expand Down Expand Up @@ -51,6 +52,6 @@ class mlp_int8_system : public sc_module {
mlp_driver* mlp_driver_inst;
mlp_top* mlp_inst;

mlp_int8_system(const sc_module_name& name, sc_clock* driver_clk_sig);
mlp_int8_system(const sc_module_name& name, sc_clock* driver_clk_sig, RADSimDesignContext* radsim_design);
~mlp_int8_system();
};
20 changes: 11 additions & 9 deletions rad-sim/example-designs/mlp_int8/mlp_top.cpp
Original file line number Diff line number Diff line change
@@ -1,9 +1,10 @@
#include <mlp_top.hpp>

mlp_top::mlp_top(const sc_module_name &name) : sc_module(name) {
mlp_top::mlp_top(const sc_module_name &name, RADSimDesignContext* radsim_design) : design_top(radsim_design) {
this->radsim_design = radsim_design;

std::string design_root_dir =
radsim_config.GetStringKnob("radsim_user_design_root_dir");
radsim_config.GetStringKnobPerRad("radsim_user_design_root_dir", radsim_design->rad_id);
std::string design_config_filename =
design_root_dir + "/compiler/layer_mvm_config";

Expand Down Expand Up @@ -66,7 +67,7 @@ mlp_top::mlp_top(const sc_module_name &name) : sc_module(name) {
for (unsigned int mvm_id = 0; mvm_id < num_mvms_total[0]; mvm_id++) {
module_name_str = "input_dispatcher" + std::to_string(mvm_id);
std::strcpy(module_name, module_name_str.c_str());
input_dispatchers[mvm_id] = new dispatcher(module_name, mvm_id);
input_dispatchers[mvm_id] = new dispatcher(module_name, mvm_id, radsim_design);
input_dispatchers[mvm_id]->rst(rst);
input_dispatchers[mvm_id]->data_fifo_rdy(dispatcher_fifo_rdy[mvm_id]);
input_dispatchers[mvm_id]->data_fifo_wen(dispatcher_fifo_wen[mvm_id]);
Expand All @@ -76,15 +77,15 @@ mlp_top::mlp_top(const sc_module_name &name) : sc_module(name) {

module_name_str = "output_collector";
std::strcpy(module_name, module_name_str.c_str());
output_collector = new collector(module_name);
output_collector = new collector(module_name, radsim_design);
output_collector->rst(rst);
output_collector->data_fifo_rdy(collector_fifo_rdy);
output_collector->data_fifo_ren(collector_fifo_ren);
output_collector->data_fifo_rdata(collector_fifo_rdata);

module_name_str = "weight_loader";
std::strcpy(module_name, module_name_str.c_str());
wloader = new weight_loader(module_name);
wloader = new weight_loader(module_name, radsim_design);
wloader->rst(rst);
wloader->weight_fifo_rdy(weight_loader_weight_fifo_rdy);
wloader->weight_fifo_wen(weight_loader_weight_fifo_wen);
Expand All @@ -104,7 +105,7 @@ mlp_top::mlp_top(const sc_module_name &name) : sc_module(name) {

module_name_str = "inst_loader";
std::strcpy(module_name, module_name_str.c_str());
iloader = new inst_loader(module_name);
iloader = new inst_loader(module_name, radsim_design);
iloader->rst(rst);
iloader->inst_fifo_rdy(inst_loader_inst_fifo_rdy);
iloader->inst_fifo_wen(inst_loader_inst_fifo_wen);
Expand All @@ -116,9 +117,10 @@ mlp_top::mlp_top(const sc_module_name &name) : sc_module(name) {
iloader->mvm_id_fifo_wen(inst_loader_mvm_id_fifo_wen);
iloader->mvm_id_fifo_wdata(inst_loader_mvm_id_fifo_wdata);

radsim_design.BuildDesignContext("mlp.place", "mlp.clks");
radsim_design.CreateSystemNoCs(rst);
radsim_design.ConnectModulesToNoC();
this->portal_inst->rst(rst);
radsim_design->BuildDesignContext("mlp.place", "mlp.clks");
radsim_design->CreateSystemNoCs(rst);
radsim_design->ConnectModulesToNoC();
}

mlp_top::~mlp_top() {
Expand Down
6 changes: 4 additions & 2 deletions rad-sim/example-designs/mlp_int8/mlp_top.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,10 @@
#include <sim_utils.hpp>
#include <design_context.hpp>
#include <radsim_config.hpp>
#include <design_top.hpp>


class mlp_top : public sc_module {
class mlp_top : public design_top {
private:
std::vector<std::vector<rtl_mvm*>> rtl_matrix_vector_engines;
std::vector<std::vector<sysc_mvm*>> sysc_matrix_vector_engines;
Expand All @@ -24,6 +25,7 @@ class mlp_top : public sc_module {
collector* output_collector;
weight_loader* wloader;
inst_loader* iloader;
RADSimDesignContext* radsim_design;

public:
sc_in<bool> rst;
Expand Down Expand Up @@ -62,7 +64,7 @@ class mlp_top : public sc_module {
sc_in<bool> collector_fifo_ren;
sc_out<data_vector<sc_int<IPRECISION>>> collector_fifo_rdata;

mlp_top(const sc_module_name& name);
mlp_top(const sc_module_name& name, RADSimDesignContext* radsim_design);
~mlp_top();
void prepare_adapters_info();
};
Loading

0 comments on commit ce1670b

Please sign in to comment.