Cleaned up variable and function names, etc

rad-sim/config.py

@@ -33,10 +33,6 @@ def parse_config_file(config_filename, booksim_params, radsim_header_params, rad
                     if param_name in radsim_knobs[config_counter]:
                         radsim_knobs[config_counter][param_name] = param_value
                         invalid_param = False
-                    # if param_name == "dram_config_files": #TODO: double check dram_config_files correct, had error earlier but I think I fixed earlier
-                    #     print('param_value')
-                    #     print(config_counter)
-                    #     print(param_value)
 
                     if invalid_param:
                         print("Config Error: Parameter " + param_name + " is invalid!")
@@ -265,12 +261,12 @@ def generate_radsim_params_header(radsim_header_params):
         str(radsim_header_params["interfaces_axi_user_width"]) + "\n")
 
     radsim_params_header_file.write("// (Almost always) Constant AXI Parameters\n")
-    radsim_params_header_file.write("// NOTE: AXIS_DEST_FIELDW must be NOC_LINKS_DEST_WIDTH/3 to fit RAD_DEST_ID, REMOTE_NODE_ID, and LOCAL_NODE_ID\n")
     radsim_params_header_file.write("#define AXIS_STRBW  " + str(radsim_header_params["interfaces_axis_tstrb_width"]) + "\n")
     radsim_params_header_file.write("#define AXIS_KEEPW  " + str(radsim_header_params["interfaces_axis_tkeep_width"]) + "\n")
     radsim_params_header_file.write("#define AXIS_IDW    NOC_LINKS_PACKETID_WIDTH\n")
     radsim_params_header_file.write("#define AXIS_DESTW  NOC_LINKS_DEST_WIDTH\n")
-    radsim_params_header_file.write("#define AXIS_DEST_FIELDW  " + str(max_destination_field_bitwidth) + "\n") # TO-DO-MR: Define parameter for destination field width (to separate 3 fields)
+    #NOTE: AXIS_DEST_FIELDW is NOC_LINKS_DEST_WIDTH/3 to fit RAD_DEST_ID, REMOTE_NODE_ID, and LOCAL_NODE_ID
+    radsim_params_header_file.write("#define AXIS_DEST_FIELDW  " + str(max_destination_field_bitwidth) + "\n")
     radsim_params_header_file.write("#define AXI4_IDW    " + str(radsim_header_params["interfaces_axi_id_width"]) + "\n")
     radsim_params_header_file.write("#define AXI4_ADDRW  64\n")
     radsim_params_header_file.write("#define AXI4_LENW   8\n")
@@ -333,11 +329,11 @@ def get_fraction(input_val):
 
 def generate_radsim_config_file(radsim_knobs, cluster_knobs):
     radsim_config_file = open(radsim_header_params["radsim_root_dir"] + "/sim/radsim_knobs", "w")
-    for i in range(len(cluster_knobs["cluster_configs"])):
-        curr_config_name = cluster_knobs["cluster_configs"][i] #retrieve the config num by rad ID
+    for config_id in range(len(cluster_knobs["cluster_configs"])):
+        curr_config_name = cluster_knobs["cluster_configs"][config_id] #retrieve the config num by rad ID
         curr_config_num = config_names.index(curr_config_name)
-        for param in radsim_knobs[i]:
-            radsim_config_file.write(param + " " + str(i) + " ") # second element is RAD ID
+        for param in radsim_knobs[config_id]:
+            radsim_config_file.write(param + " " + str(config_id) + " ") # second element is RAD ID
             if isinstance(radsim_knobs[curr_config_num][param], list):
                 for value in radsim_knobs[curr_config_num][param]:
                     radsim_config_file.write(str(value) + " ")
@@ -412,7 +408,7 @@ def generate_radsim_main(design_names, radsim_knobs):
         main_cpp_file.write("\t\t\"node_clk0\", radsim_config.GetDoubleKnobShared(\"sim_driver_period\"), SC_NS);\n")
         main_cpp_file.write("\tRADSimInterRad* blackbox = new RADSimInterRad(\"inter_rad_box\", inter_rad_clk_sig, cluster);\n\n")
         for i in range(cluster_knobs["num_rads"]):
-            main_cpp_file.write("\tblackbox->ConnectRadAxi(" + str(i) +");\n")
+            main_cpp_file.write("\tblackbox->ConnectClusterInterfaces(" + str(i) +");\n")
     #main_cpp_file.write("\tsc_start();\n\n")
     main_cpp_file.write("\n\tint start_cycle = GetSimulationCycle(radsim_config.GetDoubleKnobShared(\"sim_driver_period\"));\n")
     main_cpp_file.write("\twhile (cluster->AllRADsNotDone()) {\n")

rad-sim/config.yml

@@ -1,16 +1,40 @@
+config rad1:
+  dram:
+    num_controllers: 4
+    clk_periods: [3.32, 3.32, 2.0, 2.0]
+    queue_sizes: [64, 64, 64, 64]
+    config_files: ['DDR4_8Gb_x16_2400', 'DDR4_8Gb_x16_2400', 'HBM2_8Gb_x128', 'HBM2_8Gb_x128']
+
+  design:
+    name: 'dlrm_two_rad'
+    noc_placement: ['dlrm_two_rad.place']
+    clk_periods: [5.0, 2.0, 3.32, 1.5]
+
+config anotherconfig:
+  dram:
+    num_controllers: 4
+    clk_periods: [3.32, 3.32, 2.0, 2.0]
+    queue_sizes: [64, 64, 64, 64]
+    config_files: ['DDR4_8Gb_x16_2400', 'DDR4_8Gb_x16_2400', 'HBM2_8Gb_x128', 'HBM2_8Gb_x128']
+
+  design:
+    name: 'dlrm_two_rad'
+    noc_placement: ['dlrm_two_rad.place']
+    clk_periods: [5.0, 2.0, 3.32, 1.5]
+
 noc:
   type: ['2d']
   num_nocs: 1
   clk_period: [1.0]
-  payload_width: [145]
+  payload_width: [82]
   topology: ['mesh']
-  dim_x: [4]
-  dim_y: [4] 
+  dim_x: [10]
+  dim_y: [10] 
   routing_func: ['dim_order']
-  vcs: [1]
-  vc_buffer_size: [8]
+  vcs: [5]
+  vc_buffer_size: [16]
   output_buffer_size: [8]
-  num_packet_types: [1]
+  num_packet_types: [5]
   router_uarch: ['iq']
   vc_allocator: ['islip']
   sw_allocator:  ['islip']
@@ -27,19 +51,13 @@ noc_adapters:
   out_arbiter: ['priority_rr']
   vc_mapping: ['direct']
 
-config rad1:
-        design:
-                name: 'mlp'
-                noc_placement: ['mlp.place']
-                clk_periods: [5.0]
-
-cluster:
-        sim_driver_period: 5.0
-        telemetry_log_verbosity: 2
-        telemetry_traces: []
-        num_rads: 1
-        cluster_configs: ['rad1']
-
-interfaces:
-  max_axis_tdata_width: 512
-  axis_tuser_width: 75
+cluster:  
+  sim_driver_period: 5.0
+  telemetry_log_verbosity: 2
+  telemetry_traces: ['Embedding LU', 'Mem0', 'Mem1', 'Mem2', 'Mem3', 'Feature Inter.', 'MVM first', 'MVM last']
+  num_rads: 2
+  cluster_configs: ['rad1', 'anotherconfig']
+  cluster_topology: 'all-to-all'
+  inter_rad_latency: 2100
+  inter_rad_bw: 102.4
+  inter_rad_fifo_num_slots: 1000

rad-sim/example-designs/dlrm/compiler/dlrm.py

@@ -782,6 +782,8 @@ def generate_dlrm_defines_hpp():
     dlrm_defines.write("#define INST_MEM_DEPTH 2048\n")
     dlrm_defines.write("#define DOT_PRODUCTS LANES\n")
     dlrm_defines.write("#define DATAW (BITWIDTH * LANES)\n")
+    dlrm_defines.write("#define TDATA_ELEMS 32\n")
+    dlrm_defines.write("#define TDATA_WIDTH 16\n")
     dlrm_defines.close()
 
 

rad-sim/example-designs/dlrm/modules/dlrm_defines.hpp

@@ -7,3 +7,5 @@
 #define INST_MEM_DEPTH 2048
 #define DOT_PRODUCTS LANES
 #define DATAW (BITWIDTH * LANES)
+#define TDATA_ELEMS 32
+#define TDATA_WIDTH 16

rad-sim/example-designs/dlrm/modules/mvm.cpp

@@ -315,11 +315,11 @@ void mvm::Tick() {
 
     if (rx_input_interface.tvalid.read() && rx_input_interface.tready.read()) {
       sc_bv<AXIS_MAX_DATAW> tdata = rx_input_interface.tdata.read();
-      data_vector<int16_t> tdatavector(32);
+      data_vector<int16_t> tdatavector(TDATA_ELEMS);
       unsigned int start_idx, end_idx;
-      for (unsigned int e = 0; e < 32; e++) {
-        start_idx = e * 16;
-        end_idx = (e + 1) * 16;
+      for (unsigned int e = 0; e < TDATA_ELEMS; e++) {
+        start_idx = e * TDATA_WIDTH;
+        end_idx = (e + 1) * TDATA_WIDTH;
         tdatavector[e] = tdata.range(end_idx - 1, start_idx).to_int();
       }
 

rad-sim/example-designs/dlrm_two_rad/compiler/dlrm.py

@@ -782,6 +782,8 @@ def generate_dlrm_defines_hpp():
     dlrm_defines.write("#define INST_MEM_DEPTH 2048\n")
     dlrm_defines.write("#define DOT_PRODUCTS LANES\n")
     dlrm_defines.write("#define DATAW (BITWIDTH * LANES)\n")
+    dlrm_defines.write("#define TDATA_ELEMS 32\n")
+    dlrm_defines.write("#define TDATA_WIDTH 16\n")
     dlrm_defines.close()
 
 

rad-sim/example-designs/dlrm_two_rad/modules/dlrm_defines.hpp

@@ -7,3 +7,5 @@
 #define INST_MEM_DEPTH 2048
 #define DOT_PRODUCTS LANES
 #define DATAW (BITWIDTH * LANES)
+#define TDATA_ELEMS 32
+#define TDATA_WIDTH 16

rad-sim/example-designs/dlrm_two_rad/modules/mvm.cpp

@@ -316,16 +316,14 @@ void mvm::Tick() {
 
     if (rx_input_interface.tvalid.read() && rx_input_interface.tready.read()) {
       sc_bv<AXIS_MAX_DATAW> tdata = rx_input_interface.tdata.read();
-      data_vector<int16_t> tdatavector(32);
+      data_vector<int16_t> tdatavector(TDATA_ELEMS);
       unsigned int start_idx, end_idx;
-      for (unsigned int e = 0; e < 32; e++) {
-        start_idx = e * 16;
-        end_idx = (e + 1) * 16;
+      for (unsigned int e = 0; e < TDATA_ELEMS; e++) {
+        start_idx = e * TDATA_WIDTH;
+        end_idx = (e + 1) * TDATA_WIDTH;
         tdatavector[e] = tdata.range(end_idx - 1, start_idx).to_int();
       }
-      //if (layer_id == 0) std::cout << "got tdatavector on rad " << radsim_design->rad_id << ": " << tdatavector << std::endl;
-      // sc_bv<7> testing_width = "1000110";
-      // std::cout << "testing_width.to_uint64(): " << testing_width.to_uint64() << std::endl;
+
       if (rx_input_interface.tuser.read().range(15, 13).to_uint() == 1) {
         unsigned int waddr =
             rx_input_interface.tuser.read().range(8, 0).to_uint();

rad-sim/example-designs/npu/compiler/09_std_rnn_1536_8.py

@@ -0,0 +1,41 @@
+import os
+os.environ["CUDA_VISIBLE_DEVICES"] = "-1"
+os.environ['TF_CPP_MIN_LOG_LEVEL'] = "2"
+import tensorflow as tf
+from tensorflow import keras
+from tensorflow.keras import layers
+#import sys
+#sys.path.append('../compiler/')
+
+from compiler import *
+from npu_layers import *
+
+###### START OF MODEL DEFINITION ######
+
+# Define constants
+INPUT_SIZE = 1536
+HIDDEN_UNITS = 1536
+TIME_STEPS = 8
+
+# Define model architecture using Keras Sequential Model
+model = NPUSequential([
+	layers.SimpleRNN(HIDDEN_UNITS, name="layer1"),
+])
+
+# Random test inputs for different types of layers
+test_input = tf.random.uniform(shape=[TIME_STEPS, 6, INPUT_SIZE], minval=-128, maxval=127)
+
+# Call model on example input
+y = model(test_input)
+
+# Print model summary
+model.summary()
+
+####### END OF MODEL DEFINITION #######
+
+# Initialize NPU
+npu = initialize_npu(sys.argv)
+# Compile model for NPU
+model.compile_for_npu(npu, test_input)
+# Run NPU flow
+npu.run_flow()

rad-sim/sim/main.cpp

@@ -7,7 +7,7 @@
 #include <radsim_cluster.hpp>
 #include <radsim_inter_rad.hpp>
 
-#include <mlp_system.hpp>
+#include <dlrm_two_rad_system.hpp>
 
 RADSimConfig radsim_config;
 std::ostream *gWatchOut;
@@ -17,10 +17,10 @@ SimTraceRecording sim_trace_probe;
 int sc_main(int argc, char *argv[]) {
 	std::string radsim_knobs_filename = "/sim/radsim_knobs";
 	std::string radsim_knobs_filepath = RADSIM_ROOT_DIR + radsim_knobs_filename;
-	radsim_config.ResizeAll(1);
+	radsim_config.ResizeAll(2);
 	ParseRADSimKnobs(radsim_knobs_filepath);
 
-	RADSimCluster* cluster = new RADSimCluster(1);
+	RADSimCluster* cluster = new RADSimCluster(2);
 
 	gWatchOut = &cout;
 	int log_verbosity = radsim_config.GetIntKnobShared("telemetry_log_verbosity");
@@ -31,8 +31,19 @@ int sc_main(int argc, char *argv[]) {
 
 	sc_clock *driver_clk_sig0 = new sc_clock(
 		"node_clk0", radsim_config.GetDoubleKnobShared("sim_driver_period"), SC_NS);
-	mlp_system *system0 = new mlp_system("mlp_system", driver_clk_sig0, cluster->all_rads[0]);
+	dlrm_two_rad_system *system0 = new dlrm_two_rad_system("dlrm_two_rad_system", driver_clk_sig0, cluster->all_rads[0]);
 	cluster->StoreSystem(system0);
+	sc_clock *driver_clk_sig1 = new sc_clock(
+		"node_clk0", radsim_config.GetDoubleKnobShared("sim_driver_period"), SC_NS);
+	dlrm_two_rad_system *system1 = new dlrm_two_rad_system("dlrm_two_rad_system", driver_clk_sig1, cluster->all_rads[1]);
+	cluster->StoreSystem(system1);
+
+	sc_clock *inter_rad_clk_sig = new sc_clock(
+		"node_clk0", radsim_config.GetDoubleKnobShared("sim_driver_period"), SC_NS);
+	RADSimInterRad* blackbox = new RADSimInterRad("inter_rad_box", inter_rad_clk_sig, cluster);
+
+	blackbox->ConnectClusterInterfaces(0);
+	blackbox->ConnectClusterInterfaces(1);
 
 	int start_cycle = GetSimulationCycle(radsim_config.GetDoubleKnobShared("sim_driver_period"));
 	while (cluster->AllRADsNotDone()) {
@@ -44,6 +55,11 @@ int sc_main(int argc, char *argv[]) {
 
 	delete system0;
 	delete driver_clk_sig0;
+	delete system1;
+	delete driver_clk_sig1;
+	delete blackbox;
+	delete inter_rad_clk_sig;
+
 	sc_flit scf;
 	scf.FreeAllFlits();
 	Flit *f = Flit::New();

rad-sim/sim/radsim_defines.hpp

@@ -3,14 +3,12 @@
 // clang-format off
 #define RADSIM_ROOT_DIR "/home/bassiabn/rad-sim/rad-flow/rad-sim"
 
-#define SINGLE_RAD 1
-
 // NoC-related Parameters
-#define NOC_LINKS_PAYLOAD_WIDTH   145
-#define NOC_LINKS_VCID_WIDTH      1
+#define NOC_LINKS_PAYLOAD_WIDTH   82
+#define NOC_LINKS_VCID_WIDTH      3
 #define NOC_LINKS_PACKETID_WIDTH  32
-#define NOC_LINKS_TYPEID_WIDTH    1
-#define NOC_LINKS_DEST_WIDTH      12
+#define NOC_LINKS_TYPEID_WIDTH    3
+#define NOC_LINKS_DEST_WIDTH      21
 #define NOC_LINKS_DEST_INTERFACE_WIDTH 5
 #define NOC_LINKS_WIDTH           (NOC_LINKS_PAYLOAD_WIDTH + NOC_LINKS_VCID_WIDTH         + NOC_LINKS_PACKETID_WIDTH + NOC_LINKS_DEST_WIDTH + NOC_LINKS_DEST_INTERFACE_WIDTH)
 
@@ -20,19 +18,18 @@
 #define AXIS_USERW     75
 #define AXI4_USERW     64
 // (Almost always) Constant AXI Parameters
-// NOTE: AXIS_DEST_FIELDW must be NOC_LINKS_DEST_WIDTH/3 to fit RAD_DEST_ID, REMOTE_NODE_ID, and LOCAL_NODE_ID
 #define AXIS_STRBW  8
 #define AXIS_KEEPW  8
 #define AXIS_IDW    NOC_LINKS_PACKETID_WIDTH
 #define AXIS_DESTW  NOC_LINKS_DEST_WIDTH
-#define AXIS_DEST_FIELDW  4
+#define AXIS_DEST_FIELDW  7
 #define AXI4_IDW    8
 #define AXI4_ADDRW  64
 #define AXI4_LENW   8
 #define AXI4_SIZEW  3
 #define AXI4_BURSTW 2
 #define AXI4_RESPW  2
-#define AXI4_NODE_ADDRW 4
+#define AXI4_NODE_ADDRW 7
 #define AXI4_CTRLW  (AXI4_LENW + AXI4_SIZEW + AXI4_BURSTW)
 
 // AXI Packetization Defines

rad-sim/sim/radsim_inter_rad.cpp

@@ -45,10 +45,10 @@ RADSimInterRad::~RADSimInterRad() {
 
 //Connect the axi slave interface of each portal module to its corresponding RADSimInterRad axi master interface, and vice versa
 void
-RADSimInterRad::ConnectRadAxi(int i) {
+RADSimInterRad::ConnectClusterInterfaces(int rad_id) {
     #ifndef SINGLE_RAD
-    all_axis_master_signals[i]->Connect(*(all_axis_master_ports[i]), cluster->all_systems[i]->design_dut_inst->design_top_portal_axis_slave); //Connect(axis_master_port &m, axis_slave_port &s)
-    all_axis_slave_signals[i]->Connect(cluster->all_systems[i]->design_dut_inst->design_top_portal_axis_master, *(all_axis_slave_ports[i])); //Connect(axis_master_port &m, axis_slave_port &s)
+    all_axis_master_signals[rad_id]->Connect(*(all_axis_master_ports[rad_id]), cluster->all_systems[rad_id]->design_dut_inst->design_top_portal_axis_slave);
+    all_axis_slave_signals[rad_id]->Connect(cluster->all_systems[rad_id]->design_dut_inst->design_top_portal_axis_master, *(all_axis_slave_ports[rad_id]));
     #endif
 }
 

rad-sim/sim/radsim_inter_rad.hpp

@@ -52,7 +52,7 @@ class RADSimInterRad : public sc_module {
 
         RADSimInterRad(const sc_module_name &name, sc_clock *inter_rad_clk, RADSimCluster* cluster);
         ~RADSimInterRad();
-        void ConnectRadAxi(int i);
+        void ConnectClusterInterfaces(int rad_id);
         void writeFifo();
         void readFifo();
         SC_HAS_PROCESS(RADSimInterRad);