Merge pull request #22 from andrewboutros/correctness-checks

RAD-Sim Design Correctness Reporting
andrewboutros · Dec 1, 2023 · a239321 · a239321
2 parents fd857b9 + ec92d85
commit a239321
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Showing 9 changed files with 40 additions and 11 deletions.
diff --git a/rad-sim/config.py b/rad-sim/config.py
@@ -294,7 +294,7 @@ def generate_radsim_main(design_name):
     main_cpp_file.write("\tsim_trace_probe.dump_traces();\n")
     main_cpp_file.write("\t(void)argc;\n")
     main_cpp_file.write("\t(void)argv;\n")
-    main_cpp_file.write("\treturn 0;\n")
+    main_cpp_file.write("\treturn radsim_design.GetSimExitCode();\n")
     main_cpp_file.write("}\n")
 
 def prepare_build_dir(design_name):

diff --git a/rad-sim/example-designs/add/add_driver.cpp b/rad-sim/example-designs/add/add_driver.cpp
@@ -58,8 +58,12 @@ void add_driver::sink() {
   //std::cout << "Received " << response.read().to_uint64() << " sum from the adder!" << std::endl;
   //std::cout << "The actual sum is " << actual_sum << std::endl;
 
-  if (response.read() != actual_sum) std::cout << "FAILURE - Output is not matching!" << std::endl;
-  else std::cout << "SUCCESS - Output is matching!" << std::endl;
+  if (response.read() != actual_sum) {
+    std::cout << "FAILURE - Output is not matching!" << std::endl;
+    radsim_design.ReportDesignFailure();
+  } else {
+    std::cout << "SUCCESS - Output is matching!" << std::endl;
+  }
 
   end_cycle = GetSimulationCycle(radsim_config.GetDoubleKnob("sim_driver_period"));
   end_time = std::chrono::steady_clock::now();

diff --git a/rad-sim/example-designs/dlrm/dlrm_driver.cpp b/rad-sim/example-designs/dlrm/dlrm_driver.cpp
@@ -194,8 +194,8 @@ void dlrm_driver::sink() {
   if (all_outputs_matching) {
     std::cout << "Simulation PASSED! All outputs matching!" << std::endl;
   } else {
-    std::cout << "Simulation FAILED! Some outputs are NOT matching!"
-              << std::endl;
+    std::cout << "Simulation FAILED! Some outputs are NOT matching!" << std::endl;
+    radsim_design.ReportDesignFailure();
   }
   _end_cycle =
       GetSimulationCycle(radsim_config.GetDoubleKnob("sim_driver_period"));

diff --git a/rad-sim/example-designs/mlp/mlp_driver.cpp b/rad-sim/example-designs/mlp/mlp_driver.cpp
@@ -126,7 +126,10 @@ void mlp_driver::sink() {
     }
     wait();
   }
-  if (mistake) std::cout << "FAILURE - Some outputs NOT matching!" << std::endl;
+  if (mistake) {
+    std::cout << "FAILURE - Some outputs NOT matching!" << std::endl;
+    radsim_design.ReportDesignFailure();
+  }
   else std::cout << "SUCCESS - All outputs are matching!" << std::endl;
 
   end_cycle = GetSimulationCycle(radsim_config.GetDoubleKnob("sim_driver_period"));

diff --git a/rad-sim/example-designs/mlp_int8/mlp_driver.cpp b/rad-sim/example-designs/mlp_int8/mlp_driver.cpp
@@ -307,14 +307,19 @@ void mlp_driver::sink() {
     }
     wait();
   }
-  if (mistake) std::cout << "FAILURE - Some outputs NOT matching!" << std::endl;
-  else std::cout << "SUCCESS - All outputs are matching!" << std::endl;
+  if (mistake) {
+    std::cout << "FAILURE - Some outputs NOT matching!" << std::endl;
+    radsim_design.ReportDesignFailure();
+  } else {
+    std::cout << "SUCCESS - All outputs are matching!" << std::endl;
+  }
 
   end_cycle = GetSimulationCycle(radsim_config.GetDoubleKnob("sim_driver_period"));
   end_time = std::chrono::steady_clock::now();
   std::cout << "Simulation Cycles = " << end_cycle - start_cycle << std::endl;
   std::cout << "Simulation Time = " << std::chrono::duration_cast<std::chrono::milliseconds> (end_time - start_time).count() << " ms" << std::endl;
   NoCTransactionTelemetry::DumpStatsToFile("stats.csv");
+  NoCFlitTelemetry::DumpNoCFlitTracesToFile("flit_traces.csv");
 
   std::vector<double> aggregate_bandwidths = NoCTransactionTelemetry::DumpTrafficFlows("traffic_flows", 
     end_cycle - start_cycle, radsim_design.GetNodeModuleNames());

diff --git a/rad-sim/example-designs/rtl_add/rtl_add_driver.cpp b/rad-sim/example-designs/rtl_add/rtl_add_driver.cpp
@@ -58,8 +58,12 @@ void rtl_add_driver::sink() {
   //std::cout << "Received " << response.read().to_uint64() << " sum from the adder!" << std::endl;
   //std::cout << "The actual sum is " << actual_sum << std::endl;
 
-  if (response.read() != actual_sum) std::cout << "FAILURE - Output is not matching!" << std::endl;
-  else std::cout << "SUCCESS - Output is matching!" << std::endl;
+  if (response.read() != actual_sum) {
+    std::cout << "FAILURE - Output is not matching!" << std::endl;
+    radsim_design.ReportDesignFailure();
+  } else {
+    std::cout << "SUCCESS - Output is matching!" << std::endl;
+  }
 
   end_cycle = GetSimulationCycle(radsim_config.GetDoubleKnob("sim_driver_period"));
   end_time = std::chrono::steady_clock::now();

diff --git a/rad-sim/sim/design_context.cpp b/rad-sim/sim/design_context.cpp
@@ -688,4 +688,12 @@ uint64_t RADSimDesignContext::GetPortBaseAddress(std::string &port_name) {
   assert(_aximm_port_base_addresses.find(port_name) !=
          _aximm_port_base_addresses.end());
   return _aximm_port_base_addresses[port_name];
+}
+
+int RADSimDesignContext::GetSimExitCode() {
+  return _sim_exit_code;
+}
+
+void RADSimDesignContext::ReportDesignFailure() {
+  _sim_exit_code = 1;
 }
diff --git a/rad-sim/sim/design_context.hpp b/rad-sim/sim/design_context.hpp
@@ -12,6 +12,8 @@
 
 class RADSimDesignContext {
 private:
+  int _sim_exit_code = 0;
+
   std::vector<sc_clock *> _noc_clks;
   std::vector<sc_clock *> _adapter_clks;
   std::vector<sc_clock *> _module_clks;
@@ -96,6 +98,9 @@ class RADSimDesignContext {
   void DumpDesignContext();
   std::vector<std::vector<std::set<std::string>>> &GetNodeModuleNames();
   uint64_t GetPortBaseAddress(std::string &port_name);
+
+  int GetSimExitCode();
+  void ReportDesignFailure();
 };
 
 extern RADSimDesignContext radsim_design;
diff --git a/rad-sim/sim/main.cpp b/rad-sim/sim/main.cpp
@@ -38,5 +38,5 @@ int sc_main(int argc, char *argv[]) {
 	sim_trace_probe.dump_traces();
 	(void)argc;
 	(void)argv;
-	return 0;
+	return radsim_design.GetSimExitCode();
 }