Merge pull request #13 from andrewboutros/dev-gtrieu

Automatic Wrapper Generation / RAD-Sim C++17 enable

.github/workflows/rad_sim_ci.yml

@@ -9,7 +9,35 @@ on:
   pull_request:
     branches: [ "main" ]
 
+permissions:
+  contents: read
+  actions: read
+  checks: write
+
 jobs:
+  script-tests:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v3
+
+    - uses: actions/setup-python@v4
+      with:
+        python-version: '3.10'
+        cache: 'pip'
+
+    - name: Run Python Tests for RAD-Sim scripts
+      working-directory: rad-sim
+      run: |
+        pip install -r test/requirements.txt
+        python -m xmlrunner discover . --output-file test/test-report.xml
+
+    - name: Test Summary
+      uses: test-summary/action@v2
+      if: always()
+      with:
+        paths: "rad-sim/test/*report.xml"
+        show: "all"
+
   build:
     runs-on: ubuntu-latest
     defaults:

rad-sim/.gitignore

@@ -1,3 +1,6 @@
 .vscode
 .DS_store
-radsim_knobs
+radsim_knobs
+__pycache__
+
+test/*.xml

rad-sim/CMakeLists.txt

@@ -1,5 +1,5 @@
 cmake_minimum_required(VERSION 3.19)
-set(CMAKE_CXX_STANDARD 11)
+set(CMAKE_CXX_STANDARD 17)
 project(RADSim)
 
 set(CMAKE_BINARY_DIR "./build/")

rad-sim/example-designs/add/modules/adder.cpp

@@ -1,7 +1,7 @@
 #include <adder.hpp>
 
 adder::adder(const sc_module_name &name)
-    : radsim_module(name) {
+    : RADSimModule(name) {
 
   // Combinational logic and its sensitivity list
   SC_METHOD(Assign);

rad-sim/example-designs/add/modules/adder.hpp

@@ -10,7 +10,7 @@
 #include <systemc.h>
 #include <vector>
 
-class adder : public radsim_module {
+class adder : public RADSimModule {
 private:
   sc_bv<DATAW> adder_rolling_sum; // Sum to store result
   sc_signal<bool> t_finished; // Signal flagging that the transaction has terminated

rad-sim/example-designs/add/modules/client.cpp

@@ -1,7 +1,7 @@
 #include <client.hpp>
 
 client::client(const sc_module_name &name, unsigned int fifo_depth)
-    : radsim_module(name) {
+    : RADSimModule(name) {
 
   client_fifo_depth = fifo_depth;
 

rad-sim/example-designs/add/modules/client.hpp

@@ -11,7 +11,7 @@
 
 #define DATAW 128
 
-class client : public radsim_module {
+class client : public RADSimModule {
 private:
   std::queue<sc_bv<DATAW>> client_tdata_fifo; // FIFO to store numbers
   unsigned int client_fifo_depth;    // MAXIMUM number of addends to store in FIFO

rad-sim/example-designs/rtl_add/CMakeLists.txt

@@ -14,22 +14,20 @@ include_directories(
 )
 
 set(srcfiles
-  modules/adder_wrapper.cpp
-  modules/client_wrapper.cpp
+  modules/adder.cpp
+  modules/client.cpp
   rtl_add_top.cpp
   rtl_add_driver.cpp
   rtl_add_system.cpp
 )
 
 set(hdrfiles
-  modules/adder_wrapper.hpp
-  modules/client_wrapper.hpp
+  modules/adder.hpp
+  modules/client.hpp
   rtl_add_top.hpp
   rtl_add_driver.hpp
   rtl_add_system.hpp
 )
 
-add_compile_options(-Wall -Wextra -pedantic)
-
 add_library(design STATIC ${srcfiles} ${hdrfiles})
 target_link_libraries(design PUBLIC SystemC::systemc booksim noc rtl_designs)

rad-sim/example-designs/rtl_add/modules/adder.cpp

@@ -0,0 +1,28 @@
+#include <Vadder.h>
+#include <adder.hpp>
+
+adder::adder(const sc_module_name &name) : RADSimModule(name) {
+	Vadder* vadder = new Vadder{"vadder"};
+	vadder->clk(clk);
+	vadder->rst(rst);
+	vadder->axis_adder_interface_tvalid(axis_adder_interface.tvalid);
+	vadder->axis_adder_interface_tlast(axis_adder_interface.tlast);
+	vadder->axis_adder_interface_tdata(axis_adder_interface.tdata);
+	vadder->axis_adder_interface_tready(axis_adder_interface.tready);
+	vadder->response(response);
+	vadder->response_valid(response_valid);
+
+	this->RegisterModuleInfo();
+}
+
+adder::~adder() {}
+
+void adder::RegisterModuleInfo() {
+	std::string port_name;
+	_num_noc_axis_slave_ports = 0;
+	_num_noc_axis_master_ports = 0;
+	_num_noc_aximm_slave_ports = 0;
+	_num_noc_aximm_master_ports = 0;
+	port_name = module_name + ".axis_adder_interface";
+	RegisterAxisSlavePort(port_name, &axis_adder_interface, 128, 0);
+}

rad-sim/example-designs/rtl_add/modules/adder.hpp

@@ -0,0 +1,24 @@
+#pragma once
+
+#include <axis_interface.hpp>
+#include <design_context.hpp>
+#include <radsim_defines.hpp>
+#include <radsim_module.hpp>
+#include <string>
+#include <systemc.h>
+#include <vector>
+
+class adder : public RADSimModule {
+public:
+	sc_in<bool> rst;
+	sc_out<sc_bv<128>> response;
+	sc_out<bool> response_valid;
+
+	axis_slave_port axis_adder_interface;
+
+	adder(const sc_module_name &name);
+	~adder();
+
+	SC_HAS_PROCESS(adder);
+	void RegisterModuleInfo();
+};

rad-sim/example-designs/rtl_add/modules/client.cpp

@@ -0,0 +1,35 @@
+#include <Vclient.h>
+#include <client.hpp>
+
+client::client(const sc_module_name &name) : RADSimModule(name) {
+	Vclient* vclient = new Vclient{"vclient"};
+	vclient->clk(clk);
+	vclient->rst(rst);
+	vclient->client_tdata(client_tdata);
+	vclient->client_tlast(client_tlast);
+	vclient->client_valid(client_valid);
+	vclient->axis_client_interface_tready(axis_client_interface.tready);
+	vclient->client_ready(client_ready);
+	vclient->axis_client_interface_tvalid(axis_client_interface.tvalid);
+	vclient->axis_client_interface_tlast(axis_client_interface.tlast);
+	vclient->axis_client_interface_tdest(axis_client_interface.tdest);
+	vclient->axis_client_interface_tid(axis_client_interface.tid);
+	vclient->axis_client_interface_tstrb(axis_client_interface.tstrb);
+	vclient->axis_client_interface_tkeep(axis_client_interface.tkeep);
+	vclient->axis_client_interface_tuser(axis_client_interface.tuser);
+	vclient->axis_client_interface_tdata(axis_client_interface.tdata);
+
+	this->RegisterModuleInfo();
+}
+
+client::~client() {}
+
+void client::RegisterModuleInfo() {
+	std::string port_name;
+	_num_noc_axis_slave_ports = 0;
+	_num_noc_axis_master_ports = 0;
+	_num_noc_aximm_slave_ports = 0;
+	_num_noc_aximm_master_ports = 0;
+	port_name = module_name + ".axis_client_interface";
+	RegisterAxisMasterPort(port_name, &axis_client_interface, 128, 0);
+}

rad-sim/example-designs/rtl_add/modules/client.hpp

@@ -0,0 +1,26 @@
+#pragma once
+
+#include <axis_interface.hpp>
+#include <design_context.hpp>
+#include <radsim_defines.hpp>
+#include <radsim_module.hpp>
+#include <string>
+#include <systemc.h>
+#include <vector>
+
+class client : public RADSimModule {
+public:
+	sc_in<bool> rst;
+	sc_in<sc_bv<128>> client_tdata;
+	sc_in<bool> client_tlast;
+	sc_in<bool> client_valid;
+	sc_out<bool> client_ready;
+
+	axis_master_port axis_client_interface;
+
+	client(const sc_module_name &name);
+	~client();
+
+	SC_HAS_PROCESS(client);
+	void RegisterModuleInfo();
+};

rad-sim/example-designs/rtl_add/modules/rtl/CMakeLists.txt

@@ -18,6 +18,6 @@ foreach(module IN LISTS rtlmodules)
   verilate(rtl_designs
     SOURCES ${module}
     SYSTEMC
-    VERILATOR_ARGS --pins-bv 2 -CFLAGS -std=c++11 -Wno-fatal -Wall
+    VERILATOR_ARGS --pins-bv 2 -Wno-fatal -Wall
   )
 endforeach()

rad-sim/example-designs/rtl_add/modules/rtl/client.v

@@ -3,6 +3,9 @@
 
 `include "static_params.vh"
 
+`define DEST_ADDR `AXIS_DESTW'b0
+`define SRC_ADDR `AXIS_USERW'b11
+
 module client (
 	input clk,
 	input rst,