Fixed ported npu design to work with multi-rad code, but for single rad

rad-sim/example-designs/npu/modules/axis_inst_dispatch.cpp

@@ -69,7 +69,7 @@ axis_inst_dispatch::axis_inst_dispatch(const sc_module_name& name, unsigned int
     module_name_str = "sector_" + std::to_string(sector_id) + "_mop_axis_interface_" + std::to_string(_thread_id);
     std::strcpy(module_name, module_name_str.c_str());
     sector_mop_axis_interface[sector_id] = new axis_master_fifo_adapter<mvu_mop, sc_bv<MVU_MOP_BITWIDTH>>(
-        module_name, INSTRUCTION_INTERFACE, DEC_INSTRUCTION_INTERFACE_DATAW, 1, MVU_MOP_BITWIDTH, dest_name);
+        module_name, INSTRUCTION_INTERFACE, DEC_INSTRUCTION_INTERFACE_DATAW, 1, MVU_MOP_BITWIDTH, dest_name, radsim_design);
     sector_mop_axis_interface[sector_id]->clk(clk);
     sector_mop_axis_interface[sector_id]->rst(rst);
     sector_mop_axis_interface[sector_id]->fifo_rdy(sector_mop_rdy_signal[sector_id]);
@@ -83,7 +83,7 @@ axis_inst_dispatch::axis_inst_dispatch(const sc_module_name& name, unsigned int
     module_name_str = "evrf_" + std::to_string(sector_id) + "_mop_axis_interface_" + std::to_string(_thread_id);
     std::strcpy(module_name, module_name_str.c_str());
     evrf_mop_axis_interface[sector_id] = new axis_master_fifo_adapter<evrf_mop, sc_bv<EVRF_MOP_BITWIDTH>>(
-        module_name, INSTRUCTION_INTERFACE, DEC_INSTRUCTION_INTERFACE_DATAW, 1, EVRF_MOP_BITWIDTH, dest_name);
+        module_name, INSTRUCTION_INTERFACE, DEC_INSTRUCTION_INTERFACE_DATAW, 1, EVRF_MOP_BITWIDTH, dest_name, radsim_design);
     evrf_mop_axis_interface[sector_id]->clk(clk);
     evrf_mop_axis_interface[sector_id]->rst(rst);
     evrf_mop_axis_interface[sector_id]->fifo_rdy(evrf_mop_rdy_signal[sector_id]);
@@ -97,7 +97,7 @@ axis_inst_dispatch::axis_inst_dispatch(const sc_module_name& name, unsigned int
     module_name_str = "mfu0_" + std::to_string(sector_id) + "_mop_axis_interface_" + std::to_string(_thread_id);
     std::strcpy(module_name, module_name_str.c_str());
     mfu0_mop_axis_interface[sector_id] = new axis_master_fifo_adapter<mfu_mop, sc_bv<MFU_MOP_BITWIDTH>>(
-        module_name, INSTRUCTION_INTERFACE, DEC_INSTRUCTION_INTERFACE_DATAW, 1, MFU_MOP_BITWIDTH, dest_name);
+        module_name, INSTRUCTION_INTERFACE, DEC_INSTRUCTION_INTERFACE_DATAW, 1, MFU_MOP_BITWIDTH, dest_name, radsim_design);
     mfu0_mop_axis_interface[sector_id]->clk(clk);
     mfu0_mop_axis_interface[sector_id]->rst(rst);
     mfu0_mop_axis_interface[sector_id]->fifo_rdy(mfu0_mop_rdy_signal[sector_id]);
@@ -111,7 +111,7 @@ axis_inst_dispatch::axis_inst_dispatch(const sc_module_name& name, unsigned int
     module_name_str = "mfu1_" + std::to_string(sector_id) + "_mop_axis_interface_" + std::to_string(_thread_id);
     std::strcpy(module_name, module_name_str.c_str());
     mfu1_mop_axis_interface[sector_id] = new axis_master_fifo_adapter<mfu_mop, sc_bv<MFU_MOP_BITWIDTH>>(
-        module_name, INSTRUCTION_INTERFACE, DEC_INSTRUCTION_INTERFACE_DATAW, 1, MFU_MOP_BITWIDTH, dest_name);
+        module_name, INSTRUCTION_INTERFACE, DEC_INSTRUCTION_INTERFACE_DATAW, 1, MFU_MOP_BITWIDTH, dest_name, radsim_design);
     mfu1_mop_axis_interface[sector_id]->clk(clk);
     mfu1_mop_axis_interface[sector_id]->rst(rst);
     mfu1_mop_axis_interface[sector_id]->fifo_rdy(mfu1_mop_rdy_signal[sector_id]);
@@ -125,7 +125,7 @@ axis_inst_dispatch::axis_inst_dispatch(const sc_module_name& name, unsigned int
   module_name_str = "ld_mop_axis_interface_" + std::to_string(_thread_id);
   std::strcpy(module_name, module_name_str.c_str());
   ld_mop_axis_interface = new axis_master_fifo_adapter<ld_mop, sc_bv<LD_MOP_BITWIDTH>>(
-      module_name, INSTRUCTION_INTERFACE, DEC_INSTRUCTION_INTERFACE_DATAW, 1, LD_MOP_BITWIDTH, dest_name);
+      module_name, INSTRUCTION_INTERFACE, DEC_INSTRUCTION_INTERFACE_DATAW, 1, LD_MOP_BITWIDTH, dest_name, radsim_design);
   ld_mop_axis_interface->clk(clk);
   ld_mop_axis_interface->rst(rst);
   ld_mop_axis_interface->fifo_rdy(ld_mop_rdy_signal);

rad-sim/example-designs/npu/modules/axis_mvu_sector.cpp

@@ -79,7 +79,7 @@ axis_mvu_sector::axis_mvu_sector(const sc_module_name& name, unsigned int sector
     std::strcpy(wb_interface_name, wb_interface_name_str.c_str());
     wb_axis_interface[thread_id] =
         new axis_slave_fifo_adapter<data_vector<tb_input_precision>, sc_bv<WIDE_WRITEBACK_BV_WIDTH>>(
-            wb_interface_name, MVU_WRITEBACK_INTERFACE, MVU_WRITEBACK_INTERFACE_DATAW, CORES, LOW_PRECISION, LANES);
+            wb_interface_name, MVU_WRITEBACK_INTERFACE, MVU_WRITEBACK_INTERFACE_DATAW, CORES, LOW_PRECISION, LANES, radsim_design);
     wb_axis_interface[thread_id]->clk(clk);
     wb_axis_interface[thread_id]->rst(rst);
     wb_axis_interface[thread_id]->fifo_rdy(wb_rdy_signal[thread_id]);
@@ -97,7 +97,7 @@ axis_mvu_sector::axis_mvu_sector(const sc_module_name& name, unsigned int sector
     ofifo_axis_interface[thread_id] =
         new axis_master_fifo_adapter<data_vector<tb_output_precision>, sc_bv<FEEDFORWARD_DATA_WIDTH>>(
             sector_ofifo_interface_name, FEEDFORWARD_INTERFACE, MVU_FEEDFORWARD_INTERFACE_DATAW, CORES, HIGH_PRECISION, 
-            dest_name);
+            dest_name, radsim_design);
     ofifo_axis_interface[thread_id]->clk(clk);
     ofifo_axis_interface[thread_id]->rst(rst);
     ofifo_axis_interface[thread_id]->fifo_rdy(ofifo_rdy_signal[thread_id]);
@@ -110,7 +110,7 @@ axis_mvu_sector::axis_mvu_sector(const sc_module_name& name, unsigned int sector
   char sector_name[NAME_LENGTH];
   std::string sector_name_str = "sector" + std::to_string(_sector_id);
   std::strcpy(sector_name, sector_name_str.c_str());
-  sector_module = new mvu_sector(sector_name, _sector_id);
+  sector_module = new mvu_sector(sector_name, _sector_id, radsim_design);
   sector_module->clk(clk);
   sector_module->rst(rst);
   sector_module->inst(uop_wdata_signal);

rad-sim/example-designs/npu/modules/axis_mvu_sector_chain.cpp

@@ -78,7 +78,7 @@ axis_mvu_sector_chain::axis_mvu_sector_chain(const sc_module_name& name, unsigne
     ofifo_axis_interface[thread_id] =
         new axis_master_fifo_adapter<data_vector<tb_output_precision>, sc_bv<FEEDFORWARD_DATA_WIDTH>>(
             sector_ofifo_interface_name, FEEDFORWARD_INTERFACE, MVU_FEEDFORWARD_INTERFACE_DATAW, CORES, HIGH_PRECISION,
-            dest_name);
+            dest_name, radsim_design);
     ofifo_axis_interface[thread_id]->clk(clk);
     ofifo_axis_interface[thread_id]->rst(rst);
     ofifo_axis_interface[thread_id]->fifo_rdy(ofifo_rdy_signal[thread_id]);
@@ -91,7 +91,7 @@ axis_mvu_sector_chain::axis_mvu_sector_chain(const sc_module_name& name, unsigne
   char sector_name[NAME_LENGTH];
   std::string sector_name_str = "sector" + std::to_string(_sector_id);
   std::strcpy(sector_name, sector_name_str.c_str());
-  sector_module = new mvu_sector(sector_name, _sector_id);
+  sector_module = new mvu_sector(sector_name, _sector_id, radsim_design);
   sector_module->clk(clk);
   sector_module->rst(rst);
   sector_module->inst(uop_wdata_signal);

rad-sim/example-designs/npu/modules/axis_vector_elementwise.cpp

@@ -148,7 +148,7 @@ axis_vector_elementwise::axis_vector_elementwise(const sc_module_name& name, uns
     std::strcpy(module_name, module_name_str.c_str());
     evrf_ififo_axis_interfaces[sector_id] =
         new axis_slave_fifo_adapter<data_vector<tb_output_precision>, sc_bv<FEEDFORWARD_DATA_WIDTH>>(
-            module_name, FEEDFORWARD_INTERFACE, VEW_FEEDFORWARD_INTERFACE_DATAW, CORES, HIGH_PRECISION, DPES_PER_SECTOR);
+            module_name, FEEDFORWARD_INTERFACE, VEW_FEEDFORWARD_INTERFACE_DATAW, CORES, HIGH_PRECISION, DPES_PER_SECTOR, radsim_design);
     evrf_ififo_axis_interfaces[sector_id]->clk(clk);
     evrf_ififo_axis_interfaces[sector_id]->rst(rst);
     evrf_ififo_axis_interfaces[sector_id]->fifo_rdy(evrf_ififo_rdy_signal[sector_id]);

rad-sim/example-designs/npu/modules/mvu_sector.cpp

@@ -1,6 +1,6 @@
 #include "mvu_sector.hpp"
 
-mvu_sector::mvu_sector(const sc_module_name& name, unsigned int id)
+mvu_sector::mvu_sector(const sc_module_name& name, unsigned int id, RADSimDesignContext* radsim_design)
     : sc_module(name),
       inst_valid_pipeline("inst_valid_pipeline", SECTOR_INST_TO_DPES_PIPELINE),
       inst_pipeline("inst_pipeline", SECTOR_INST_PIPELINE),
@@ -173,7 +173,7 @@ mvu_sector::mvu_sector(const sc_module_name& name, unsigned int id)
 
   mrfs.resize(DPES_PER_SECTOR);
   std::string mrf_filename, mrf_path;
-  std::string npu_dir = radsim_config.GetStringKnob("radsim_user_design_root_dir");
+  std::string npu_dir = radsim_config.GetStringKnobPerRad("radsim_user_design_root_dir", radsim_design->rad_id);
   for (unsigned int dpe_id = 0; dpe_id < DPES_PER_SECTOR; dpe_id++) {
     mrfs[dpe_id].resize(TILES);
     for (unsigned int tile_id = 0; tile_id < TILES; tile_id++) {

rad-sim/example-designs/npu/modules/mvu_sector.hpp

@@ -11,6 +11,7 @@
 #include <piso_register_file.hpp>
 #include <register_file.hpp>
 #include <dpe.hpp>
+#include <design_context.hpp>
 
 class mvu_sector : public sc_module {
  private:
@@ -92,7 +93,7 @@ class mvu_sector : public sc_module {
   sc_vector<sc_vector<sc_in<bool>>> sector_ofifo_ren;
   sc_vector<sc_vector<sc_out<data_vector<tb_output_precision>>>> sector_ofifo_rdata;
 
-  mvu_sector(const sc_module_name& name, unsigned int id);
+  mvu_sector(const sc_module_name& name, unsigned int id, RADSimDesignContext* radsim_design);
   ~mvu_sector();
 
   void Tick();

rad-sim/example-designs/npu/npu_driver.cpp

@@ -43,7 +43,7 @@ npu_driver::~npu_driver() {}
 
 void npu_driver::source() {
   bool parse_flag;
-  std::string npu_dir = radsim_config.GetStringKnob("radsim_user_design_root_dir");
+  std::string npu_dir = radsim_config.GetStringKnobPerRad("radsim_user_design_root_dir", radsim_design->rad_id);
 
   // Parse NPU instructions
   std::string inst_filename = "/register_files/instructions.txt";
@@ -181,7 +181,7 @@ void npu_driver::sink() {
   end_cycle = GetSimulationCycle(radsim_config.GetDoubleKnobShared("sim_driver_period"));
 
   std::ofstream report;
-  std::string npu_dir = radsim_config.GetStringKnob("radsim_user_design_root_dir");
+  std::string npu_dir = radsim_config.GetStringKnobPerRad("radsim_user_design_root_dir", radsim_design->rad_id);
   std::string report_filename = "/sim_done";
   std::string report_path = npu_dir + report_filename;
   report.open(report_path);

rad-sim/sim/main.cpp

@@ -7,7 +7,7 @@
 #include <radsim_cluster.hpp>
 #include <radsim_inter_rad.hpp>
 
-#include <mlp_int8_system.hpp>
+#include <npu_system.hpp>
 
 RADSimConfig radsim_config;
 std::ostream *gWatchOut;
@@ -31,7 +31,7 @@ int sc_main(int argc, char *argv[]) {
 
 	sc_clock *driver_clk_sig0 = new sc_clock(
 		"node_clk0", radsim_config.GetDoubleKnobShared("sim_driver_period"), SC_NS);
-	mlp_int8_system *system0 = new mlp_int8_system("mlp_int8_system", driver_clk_sig0, cluster->all_rads[0]);
+	npu_system *system0 = new npu_system("npu_system", driver_clk_sig0, cluster->all_rads[0]);
 	cluster->StoreSystem(system0);
 
 	sc_clock *inter_rad_clk_sig = new sc_clock(

rad-sim/sim/noc/noc0_rad0_config

@@ -1,6 +1,6 @@
 // Topology
 topology = mesh;
-k = 5;
+k = 10;
 n = 2;
 
 // Routing

rad-sim/sim/radsim_defines.hpp

@@ -8,7 +8,7 @@
 #define NOC_LINKS_VCID_WIDTH      3
 #define NOC_LINKS_PACKETID_WIDTH  32
 #define NOC_LINKS_TYPEID_WIDTH    3
-#define NOC_LINKS_DEST_WIDTH      15
+#define NOC_LINKS_DEST_WIDTH      21
 #define NOC_LINKS_DEST_INTERFACE_WIDTH 5
 #define NOC_LINKS_WIDTH           (NOC_LINKS_PAYLOAD_WIDTH + NOC_LINKS_VCID_WIDTH         + NOC_LINKS_PACKETID_WIDTH + NOC_LINKS_DEST_WIDTH + NOC_LINKS_DEST_INTERFACE_WIDTH)
 
@@ -23,14 +23,14 @@
 #define AXIS_KEEPW  8
 #define AXIS_IDW    NOC_LINKS_PACKETID_WIDTH
 #define AXIS_DESTW  NOC_LINKS_DEST_WIDTH
-#define AXIS_DEST_FIELDW  5
+#define AXIS_DEST_FIELDW  7
 #define AXI4_IDW    8
 #define AXI4_ADDRW  64
 #define AXI4_LENW   8
 #define AXI4_SIZEW  3
 #define AXI4_BURSTW 2
 #define AXI4_RESPW  2
-#define AXI4_NODE_ADDRW 5
+#define AXI4_NODE_ADDRW 7
 #define AXI4_CTRLW  (AXI4_LENW + AXI4_SIZEW + AXI4_BURSTW)
 
 // AXI Packetization Defines

rad-sim/sim/radsim_knobs

@@ -1,22 +1,22 @@
-design_name 0 mlp_int8
+design_name 0 npu
 noc_num_nocs 0 1
 noc_clk_period 0 1.0 
 noc_vcs 0 5 
 noc_payload_width 0 166 
-noc_num_nodes 0 25 
-design_noc_placement 0 mlp.place 
+noc_num_nodes 0 100 
+design_noc_placement 0 npu.place 
 noc_adapters_clk_period 0 1.25 
 noc_adapters_fifo_size 0 16 
 noc_adapters_obuff_size 0 2 
 noc_adapters_in_arbiter 0 fixed_rr 
 noc_adapters_out_arbiter 0 priority_rr 
 noc_adapters_vc_mapping 0 direct 
-design_clk_periods 0 5.0 
+design_clk_periods 0 5.0 2.5 
 dram_num_controllers 0 0
 dram_clk_periods 0 2.0 
 dram_queue_sizes 0 64 
 dram_config_files 0 HBM2_8Gb_x128 
-radsim_user_design_root_dir 0 /home/bassiabn/rad-sim/rad-flow/rad-sim/example-designs/mlp_int8
+radsim_user_design_root_dir 0 /home/bassiabn/rad-sim/rad-flow/rad-sim/example-designs/npu
 radsim_root_dir /home/bassiabn/rad-sim/rad-flow/rad-sim
 sim_driver_period 5.0
 telemetry_log_verbosity 2