feat(Other): Enable building zephyr for risc-v targets

[MaureenHelm]

Configures the zephyr build system to use the appropriate cmsis system startup and peripheral driver sources based on the target core architecture. The mxc lock driver is not implemented for risc-v and emits a build warning (which twister promotes to an error), therefore the zephyr build system is configured to build it only for arm.

Before this patch, we could only build zephyr for arm targets, but now we can build zephyr for arm or risc-v targets.

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[MaureenHelm]

@Jake-Carter can you take a look?

[Jake-Carter]

@MaureenHelm @ozersa

MAX78000 and MAX78002 also have RISC-V cores and need similar modifications.

Also, the RISC-V core needs to be booted up by the ARM core, and by default the RISC-V JTAG is not enabled. In the MSDK we have a system for dynamically linking RISC-V application on top of some basic start-up code that runs in the ARM core (see RV_ARM_Loader and the implementation here).

The implementation isn't really straightforward and involves parsing the .map file for a custom symbol added in the linker script. Is there a similar mechanism planned for Zephyr?

[Jake-Carter]

On RISC-V MXC_Lock implementation - we've had this in the TODO for a while. Let me know if we need to bump this up in priority.

[MaureenHelm]

@MaureenHelm @ozersa

MAX78000 and MAX78002 also have RISC-V cores and need similar modifications.

MAX78000 and MAX78002 don't have Zephyr ports yet. Libraries/zephyr/MAX/Source/MAX78000/CMakeLists.txt doesn't exist so there's nothing there to modify yet.

Also, the RISC-V core needs to be booted up by the ARM core, and by default the RISC-V JTAG is not enabled. In the MSDK we have a system for dynamically linking RISC-V application on top of some basic start-up code that runs in the ARM core (see RV_ARM_Loader and the implementation here).

The implementation isn't really straightforward and involves parsing the .map file for a custom symbol added in the linker script. Is there a similar mechanism planned for Zephyr?

I've implemented a different mechanism using devicetree to define the RISC-V code region, similar to some other multicore SoC families in Zephyr. The SoC boot code on the ARM core gets the RISC-V boot address from the devicetree and sets the appropriate register. Applications can use a devicetree overlay to change the region from the default if desired.