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add RFC for property labels #75
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If the goal is to produce human friendly error messages, why are these tools not using the message field? I would say we should probably not add back |
SystemVerilog assertions do not have messages in the first place; relying on messages thus limits us to yosys-based tooling on the other hand, the example given in the RFC could definitely be fixed on |
From my memory of talking to Jannis, they sort of do, in that |
I care more about Jasper than |
@jix, would you happen to have advice here? I've never used Jasper. |
We have discussed this RFC on the 2025-05-26 core subsystem meeting. The disposition was to postpone. The motivation in the RFC ( More importantly, Amaranth currently doesn't have well-defined formal semantics — there is no formal verification mode in Amaranth at all, and all formal-specific language features are essentially RTLIL legacy with no clear definition other than "what yosys and sby do". Any kind of RFC proposing features with FV justification thus has to be blocked by necessity until a formal model is proposed. |
I don't have any good advice regarding tool compatibility, I've also never used Jasper. I can confirm that using labels to identify properties seems what most FV users I've interacted with rely on, but I've also seen The SV spec defines the omission of an |
Thanks @jix! |
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