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Fix repr() of empty SingleEndedPort #1425

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Merged
merged 1 commit into from
Jun 27, 2024
Merged

Fix repr() of empty SingleEndedPort #1425

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6 changes: 3 additions & 3 deletions amaranth/lib/io.py
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Original file line number Diff line number Diff line change
Expand Up @@ -203,10 +203,10 @@ def __add__(self, other):
direction=self._direction & other._direction)

def __repr__(self):
if all(self._invert):
invert = True
elif not any(self._invert):
if not any(self._invert):
invert = False
elif all(self._invert):
invert = True
else:
invert = self._invert
return f"SingleEndedPort({self._io!r}, invert={invert!r}, direction={self._direction})"
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13 changes: 13 additions & 0 deletions tests/test_lib_io.py
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Original file line number Diff line number Diff line change
Expand Up @@ -88,6 +88,12 @@ def test_invert(self):
iport = ~port
self.assertRepr(iport, "SingleEndedPort((io-port io), invert=(False, True, False, True), direction=Direction.Output)")

def test_empty(self):
io = IOPort(1)
port = SingleEndedPort(io, invert=False)
eport = port[0:0]
self.assertRepr(eport, "SingleEndedPort((io-slice (io-port io) 0:0), invert=False, direction=Direction.Bidir)")


class DifferentialPortTestCase(FHDLTestCase):
def test_construct(self):
Expand Down Expand Up @@ -160,6 +166,13 @@ def test_invert(self):
iport = ~port
self.assertRepr(iport, "DifferentialPort((io-port iop), (io-port ion), invert=(False, True, False, True), direction=Direction.Output)")

def test_empty(self):
iop = IOPort(1)
ion = IOPort(1)
port = DifferentialPort(iop, ion, invert=False)
eport = port[0:0]
self.assertRepr(eport, "DifferentialPort((io-slice (io-port iop) 0:0), (io-slice (io-port ion) 0:0), invert=False, direction=Direction.Bidir)")


class BufferTestCase(FHDLTestCase):
def test_signature(self):
Expand Down