Skip to content

25.1 PRO Release

Compare
Choose a tag to compare
@rsantoyo1 rsantoyo1 released this 18 Apr 00:52

Release Information

Version: Release 25.1 PRO
Release Date: April 18, 2025
Device Affected: Agilex™ 5, Agilex™ 3, Agilex™ 7, Startix® 10, Arria® 10, Cyclone® V
Release Type: Mayor release/Binary release
Binary Release Path: http://releases.rocketboards.org/2025.04/

The source code and tools repositories with the current release branches or versions are shown next.

SW Component Release Repository Branch/Tag
Arm® Trusted Firmware https://github.com/altera-fpga/arm-trusted-firmware socfpga_v2.12.0/QPDS25.1_REL_GSRD_PR
U-Boot https://github.com/altera-fpga/u-boot-socfpga socfpga_v2025.01/QPDS25.1_REL_GSRD_PR
Linux kernel https://github.com/altera-fpga/linux-socfpga socfpga-6.12.11-lts/QPDS25.1_REL_GSRD_PR
Cyclone® V GHRD https://github.com/altera-fpga/cyclonev-ed-gsrd main/QPDS25.1_REL_GSRD_PR
Arria® 10 GHRD https://github.com/altera-fpga/arria10-ed-gsrd main/QPDS25.1_REL_GSRD_PR
Stratix® 10 GHRD https://github.com/altera-fpga/stratix10-ed-gsrd main/QPDS25.1_REL_GSRD_PR
Agilex™ 7 GHRD https://github.com/altera-fpga/agilex7f-ed-gsrd main/QPDS25.1_REL_GSRD_PR
Agilex™ 5 GHRD https://github.com/altera-fpga/agilex5e-ed-gsrd main/QPDS25.1_REL_GSRD_PR
GSRD https://github.com/altera-fpga/gsrd-socfpga styhead/QPDS25.1_REL_GSRD_PR
Reference Designs Sources https://github.com/altera-fpga/meta-intel-fpga-refdes styhead/QPDS25.1_REL_GSRD_PR
Reference Design Recipes https://git.yoctoproject.org/meta-intel-fpga styhead/QPDS25.1_REL_GSRD_PR
Yocto Project https://git.openembedded.org/meta-openembedded styhead
Reference Yocto Project https://git.yoctoproject.org/git/poky.git/ styhead
Baremetal Libraries https://github.com/altera-fpga/baremetal-drivers main/QPDS25.1_REL_GSRD_PR
ARM® Debugger https://www.intel.com/content/www/us/en/software-kit/846382/arm-development-studio-version-2024-1-for-intel-soc-fpga.html ARM DS 2024.1

Features Released

Feature Description Component Affected Scope
Device/Board
HSD
(Internal Use)
Discontinued building of GHRD for DK-SI-AGI027FA and DK-SI-AGI027FB development kits for Intel® Agilex™ I-Series Transceiver-SoC Development Kit (4x F-Tile). Example designs for eMMC boot for Agilex™ 7 and Stratix® 10 are no longer supported. GHRD Agilex™ 7 N/A
Enable/Disable Attestation or RSU use case based on new QSPI ownership selection. When SDM owns QSPI, attestation use case can be supported but not RSU use case. When HPS owns the QSPI, then RSU use case can be supported but not attestation. Linux Agilex™ 5 16026169736
Implement IEEE-1588v2.1 (2019) time stamp features in Ethernet TSN hard IP in addition to the 1588-v2 features. To meet the IEEE 60802 Industrial profile the IP should support 4 independent clock domains. Linux Agilex™ 5 15010611873
Create a Reference Designs demonstrating use of SDM crypto services API from FPGA and HPS as a separate modular add-on design that can builds seamlessly on top of the baseline Agilex 7 GSRD. This example should demonstrate access to crypto for SW load and other items: u-boot, ATF and Linux (to support VAB) GSRD Agilex™ 5 18025906520
Provide Linux kernel support query the ATF API version through a sysfs entry (/sys/kernel/fcs_sysfs/atf_version) Linux Agilex™ 5 18033846053
Create a series of example FPGA designs and software examples that interact with them. FPGA designs shall require no external pins or interfaces booting from SDM QSPI. Main objective is to enable users to answer the question, "how do I know that I've connected the hardware correctly and I'm accessing the CPU registers correctly? U-Boot
Linux
Agilex™ 5 14022178609
Complete support for remaining HPS peripherals, supported stacks and register settings. Extend support across bridges to FPGA soft IPs that have existing Nios HAL support with BSP. Baremetal Agilex™ 5 18039602242
Initial rebranding of eSW items from Intel to Altera (mainly Readme files this time). Also migrating GitHub repositories to atlera-fpga ATF
U-Boot
Linux
Device agnostic 14023606040
Migrate GHRD repositories to new GitHub layout on atlera-fpga GHRD Agilex™ 5
Agilex™ 7
S10
Arria® 10
Cyclone® V
14022046005
QSPI ownership is set from Quartus to decide if SDM will keep the ownership or if the ownership could be granted to the HPS. Quartus Agilex™ 5 14023286569
Support the SiPSVC V3 and new unified FCS client commands. ATF
Linux
Agilex™ 5
Agilex™ 7
S10
N5X
16026116212
16026116238
16026617451

Fixed Issues

Issue Fixed Component Affected Scope
Device/Board
HSD
(Internal Use)
Create a text file that containing the Quartuskit build number and also the git commit from the GHRD build for quick reference. Cron workflow needed to be updated. GHRD Agilex™ 5
Agilex™ 7
S10
Arria® 10
Cyclone® V
15017129225
15017295328
Need to have unique README file for each hardware design variant. GHRD Agilex™ 5 15017077043
Arria 10 GHRD ci is only producing sof and zip files. Also rbf and hps_isw_handoff is also require for GSRD. GHRD Arria® 10 15017264906
GTS IP (intel_srcss_gts) has been upgraded to v4.0.0 in 25.1. It has added one input and one output port to the IP. This caused an error in GHRD. GHRD Agilex™ 5 15017446027
U-Boot proper fails with "Synchronous Abort" when moving to socfpga_v2025.01. The issue is related to the GHRD for which the QSPI ownership is assigned by default to the SDM and needed to be changed to HPS. GHRD Agilex™ 5 15017445609
Missing .pmsf file to generate PR .rbfs. This were available in 24.3 but no longer available in 25.1. GHRD Agilex™ 7
S10
15017511373
Incorrect MPU clock rate is being reported in S10 as it's expected to be 1GHz but the actual clock rate returned is 1.2 GHz. This is a change in the GHRD from 25.1. The testcase needed to be updated to match the new clock frequency. GHRD S10 15017487322
Failing to trigger LED and response from interrupt switch in Agilex 7 I-Series devkit. Facing issue where LED unable to light up using both Linux application and webpage. Also the interrupt related to the DIP switch is not detected. However, for push button it was working ok. GHRD Agilex™ 7 15017568445
Timeout failure when applying Persona1 overlay. The error shown is FPGA manager "firmware:svc:fpga-mgr: timeout waiting for svc layer buffers". GHRD Agilex™ 7
S10
Arria® 10
15017600652
Integrate the SiPSVC V3 and new unified FCS client commands. Where FCS client can invoke SMC call asynchronously and can handle the response via callbacks(triggered on interrupt from the SDM) or via polling method from the client. This reduces latency in FCS calls. Commit IDs: 9fda9a29ba, 613daf8cb3, 8a7002e702. ATF Agilex™ 5
Agilex™ 7
S10
N5X
16026116212
16026759759
SIP SVC V3 in ATF did not taken care AES GCM related mailbox requirements in ATF. Commit IDs:59076985bc ATF Agilex 5 16026999724
16025999772
Agilex5 VAB CCERT address is not working as expected. The CCERT does not store in the allocated address. The pointer of the CCERT array is pointed to the wrong memory address. It shall point to the head of the array. Thus when send CCERT to SDM for authentication, the system is able to get the correct CCERT else it will return authentication failure. Commit IDs: c6b74311f76e. ATF Agilex™ 5 15017453043
Perform dynamic ddr memory data configuration based on hardware size when not configured in DTS. This is done based one the IO96B hardware size to initialize the memory size if user did not configure Memory range in DTS. Commit IDs: 4e4aeaad42. U-Boot Agilex™ 5 15016095242
Support full HPS boot of Agilex 7 M-Series REVB with HBM boot up HPS by removing all the FSBL HBM related handoff data. Commit IDs: e9b3afb938. U-Boot Agilex™ 7 15017340111
Migrate to the DDR IO mailbox cmd version 2: read only register and ECC Ring buffer. Commit IDs: d2d8ce15c5. U-Boot Agilex™ 5 15017211290
In the start.S file, the saved_args the default value is set to 0, but when run with ARM DS, we found the default value is some non-zero value. Commit IDs: 0abd2517c4. U-Boot Agilex™ 5 15017346429
Observed a U-Boot failure on NAND when using build 25.01. This issue was confirmed on both the mUDV and Devkit. However, when tested with the older build 24.07, U-Boot booted successfully. Error observed is: "Error code: DRAM: initcall failed at call 00000000802029a8 (err=-2)". Commit IDs: 3bb2808118. U-Boot Agilex™ 5 16026589523
Fixed compilation failure for Agilex 5 VAB with U-Boot socfpga_v2024.07 version (undefined reference to wdt_expire_now). Commit IDs: 353f8a4b3a. U-Boot Agilex™ 5 15017385094
Missing patch that affects the Cyclone V boot on U-Boot 2024.07. Commit IDs: 32378a68aa U-Boot Cyclone® V 15017434439
16023469269
Simics testcases failed in U-Boot with I3C related errors. Commit IDs: 6bd367292f, 97550dbcf1, 0ce274f898, ee8ccca929, 16ffd98fb7, afdc5be848, 74500ee5ce. U-Boot Agilex™ 5 15017431423
Fail to boot up to U-Boot with GHRD2.0 ingredient. Commit ID: 0abd2517c4. U-Boot Agilex™ 5 15017349242
Unexpected printout in U-Boot 2025.01during tftp operation. Message: "This will not be a case any time". Commit IDs: 63fd13f1b9. U-Boot Agilex™ 7 15017419683
RSU state reported as 0xf005002b when FSBL fails to launch SSBL and a WDT expiration occurs. After this implementation FSBL will report that it already started the execution with 0xf0060000. Commit IDs: 7faaf36290. U-Boot Agilex™ 5
Agilex™ 7
S10
N5X
14023897270
Failure observed in U-Boot SPL on Arria 10 adter flashing the SD Card and performing a hard reboot (power cycle). The error observed is: " Invalid bus 0 (err=-19)". Commit IDs: cd3a9044d6. U-Boot Arria® 10 15017476166
Problem running baremetal use cases after seeing problems loading the bitstream. Workaround identified. Baremetal Agilex™ 5 14024199028
14024125106
Unable to start the VSTREAM Server with ARM DS 2024.1. Workaround identified. Linux Agilex™ 5 15017133543
Link down and up consistently fails for the API call dmaengine_prep_slave_single. Error observed is " intel_fpga_eth soc@0:ssgdma_gts_0_eth eth0: Rx Next channel configuration failed". Another failure observed is: "intel_fpga_eth soc@0:ssgdma_gts_0_eth eth1: Tx: DMA write failed". Workaround identified. Linux Agilex™ 5 16026230660
16026540023
Rework FPE Implementation as per 6.12.11 to enable XGMAC (latest upstream driver). Linux Agilex™ 5 16026788956
Fixed SDOS max packet (32K-96bytes) size issue in M5 SW component. Fixed maximum packet size issue for SDOS encryption and decryption. Commit ID: 3f4374b624. Linux Agilex™ 5 16026346752
base_fpga_region is not align with upstream fpga-region in device tree (socfpga_agilex5.dtsi). Renamed from base_fpga_region to fpga-region and move outside of soc node. Commit IDs: ca7a210206. Linux Agilex™ 5 15017475448
Warning is observed when using the dd command with Linux 6.6.51. The warning may affect the performance during sdcard flashing. The warning is: dw_mmc ff808000.mmc: swiotlb buffer is full. Workaround identified. Linux Device agnostic. 15017186015
Linux RTC tests failed due to not finding /dev/rtc0. ls: /dev/rtc0: No such file or directory. Commit IDs: 120f8aa6fa, 7f35bcee11. The problem is related to the SOCFPGA-specific I2C recovery function was not invoked, leading to issues such as the SCL line being stuck in some cases. Commit IDs: 7f35bcee11, 120f8aa6fa. Linux S10 15016141215
Integrate the SiPSVC V3 and new unified FCS client commands. With the introduction of SiP SVC V3, we need to migrate the FCS client commands to this new architecture. Where FCS client can invoke SMC call asynchronously and can handle the response via callbacks(triggered on interrupt from the SDM) or via polling method from the client. There are around nearly ~60 FCS commands that we need to migrate from SiPSVC V1 to V3. Commit IDs: 64ca30ca4b, c356962595, a5c0b25fd2, 3fea1fe124. Linux Agilex™ 5 16026116238
Fix querying of physical address from virtual address for buffer payload on legacy devices using SiP SVC V3. Commit IDs: 7c8bcb360a, 3aafd432c6 Linux Agilex™ 7
S10
16026617451
If the U-Boot does not initialize the SD card before booting Linux, then Linux has issues with SD card. Specifically, when doing 'dd' with large files (up to 512MB with bs=4096 as used by board farm for example) you get IO errors, and the data gets corrupted. Commit IDs: ef87bd81cb. Linux Agilex™ 7
S10
14021514563
TSN Config 2 is not able to boot up to Linux in a 2 DK connected back to back. A hang is observed. Commit IDs: 36517151c6 Linux Agilex™ 5 15017510179
15013607416
Add support of HKDF request mailbox command. Commit IDs: d329a3b757, 3ec0714795. Linux Agilex™ 5 16026332242
Failure observed in crypto hmac when trying to differ the bin file which compare the session id and hash generated file. Commit IDs: fab2c249ff. Linux Agilex™ 7 15017576547
Failure observed when trying to boot to Linux from QSPI during RSU re-configuration after rsu update to P2. The issue arose from an incorrect QSPI address specified in the QSPI MTD device node for the SM72 device tree file. The present address of P2 overlapped with the location of the uboot.itb file in QSPI. Commit IDs: 7b3c7e9f3e. Linux Agilex™ 5 14017166971
15017476063
GSRD failed with error indicating that can't find either core.rbf or device tree under the deploy directories. This problem is related to incorrect dependencies definitions. Commit IDs: a94210d7a9, 8f7fcf1104, 30667337c0. GSRD Reference design: meta-intel-fpga-refdes Agilex™ 5
Arria® 10
18041634147
Update the FCS library and Linux crypto and security drivers to align with the changes made related to changes to match the SDM Mailbox specification for AES GCM mode. Embedded Libraries Agilex™ 5 16026472449
Agilex™ 5 debug tests hangs after ATF boot. Workaround identified. Hardware libraries. Agilex™ 5 14024199037
Patch for linux ftdi_sio support of on-board USB-Blaster 3 by completing ID_Table_Combined_Array for the ALTERA_VID and several different PID values Linux libraries Device agnostic 15017083126
Altera Bridge Freeze driver fails to be probed indicating "error -EINVAL: invalid resource (null)". Commit IDs: 2f339ea76b, c275a00557 GSRD Reference design: meta-intel-fpga-refdes Agilex™ 7
S10
15017539743
15017475906
Booting to Linux from SD Card in Xen fails. The boot fails in Linux showing the error: "mmc0: problem reading SD Status register." Commit IDs:d8fdd949f1 GSRD Reference design: meta-intel-fpga-refdes Agilex™ 7 15017574455
14011401204
Add benchmark applications to Xen: coremark, perf, stress-ng, sysbench, fio, xentop, busywork. Commit IDs: 508d6016d2. GSRD Reference design: meta-intel-fpga-refdes Agilex™ 5 15017079558
FCS client failed to validate HPS image. Fixed length and format to match VAB certificate for SDM 1.5. Commit IDs: 240f956760. FCS Application Libraries. Agilex™ 5 15017568591
Failure to apply static region in A10 PR. The failure is due to the dtb was not compiled with symbols. After applying the overlay the error observed: "OF: resolver: no symbols in root of device tree." Commits ID: c4b5eb92be. GSRD Reference design: meta-intel-fpga-refdes Arria® 10 15017600967

Known Issues

Issue Component Affected Scope
Device/Board
HSD
(Internal Use)
PR failed to get SystemID timestamp on persona0.rbf reconfiguration, returning 0 (1970-1-1 0:0:0 UTC). GHRD Agilex™ 7 15011396980
NAND driver in ATF is not functional. This affects the flows in which ATF is used as bootloader. ATF Agilex™ 5 15017037436
ATF to Linux Direct Flow fails to boot from SD Card with Agilex 5 25.1 GHRD ATF Agilex™ 5 14024688400
ATF and Baremetal are not able to boot into secure mode. These doesn't provide a method to boot into EL1 secure mode with image being executed from DDR memory. ATF
Baremetal
Agilex™ 5 14023735534
After FCS re-architecture, SDM Mailbox response for AES crypt command returns zero bytes copied to the destination buffer in update and final stage of encryption. SDM FW Agilex™ 5 15017100001
Missing ECC error injection interface in U-Boot. This is needed to verify ECC functionality from U-Boot. U-Boot Agilex™ 7 15017235029
HW design for ECC address block only allows 16-bit write on 32-bit registers. Need to modify Linux kernel EDAC driver to reflect these changes i.e. only 16-bit write is allowed on 32-bit ECC register addresses. Linux Agilex™ 5 16026027311
Warm reset fails to be applied in Linux using the reboot command having defined in the command line reboot=warm. Cold reset is observed instead. Linux Agilex™ 5
Agilex™ 7
S10
14021922100
Failure observe to send eMMC tunning data in HS400 mode from U-Boot. Linux Agilex™ 5 16025784408
16026967012
Unable to individually reset a single secondary core from another ARM core (boot-core). Linux Agilex™ 5 15013500528
Encountered an issue in A10 PR is being displaying a memory leak warning when removing persona 0, persona 1 and static region overlays in Linux. Linux Arria® 10 15017661844
Error observed in XEN after issuing the "xl create -c [email protected]" command. The error seen is "No such file or directory". Linux Agilex™ 7 15017665007
Linux get hung in crypto test when calling the command for encryption using large generated key (128mb) to do AES encrypted block mode ECB. This doesn't occur when using 4mb key. Linux Agilex™ 7 15017351283
In a MultiQSPI system, Linux is not able to create mtd partitions for any QSPI device other than CS0. Linux Agilex™ 7 14024915012
Unexpected low performance in fcs_client encryption. Need to improve the performance of the fcs client application when fetching sdos encryption. FCS Application Libraries. N5X 14021081523
Error observed fcs_client: page allocation failure for data size >200 MB. FCS Application Libraries. Agilex™ 5 15017227419

Golden System Reference Design Documentation

Examples Reference designs for the Agilex™ 5, Agilex™ 7 and Stratix® 10 are located at the Altera FPGA Developer Site.
For Arria® 10 and Cyclone® V devices, these reference designs are located at RocketBoards.

The GSRD (Golden System Reference Design) are documented in the following pages:

Agilex™ 5

Agilex™ 7

Stratix® 10

Cyclone® V

Arria® 10

Release Strategy

The HPS Embedded software releases for Intel FPGA devices are aligned with Quartus® releases and are scheduled as follows:

  • Quartus® Standard (STD): 1 release per year. This is a binary release.
  • Quartus® Pro (PRO): 4 releases per year, one each quarter. Some of these are Major release which affects most of the devices while Minor releases are released as needed and affect few devices.

Embedded software releases can also be classified as Source code or Binary releases. A Source code release involve releasing the source code in the software repositories. A Binary release consists of a source code release + pre-built binaries that could be loaded directly into the development kits.

Note: To review the Release Notes prior 24.3.1 release please refer to teh following link: https://www.rocketboards.org/foswiki/Documentation/IntelFPGAHPSEmbeddedSoftwareRelease.