Init Project

LICENCE

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+MIT LICENSE
+
+Copyright (c) 2018-present Alibaba Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be
+included in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

README.md

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+# OpenAlita
+This repository contains the source code for a research paper that was submitted for publication at the International Conference for [High Performance Computing, Networking, Storage, and Analysis](https://sc20.supercomputing.org/) (SC20). 
+
+## How to run
+
+- Split Lock Isolation
+
+    g++ test_split_lock_iso.cpp  -o test_split_lock_iso && sudo ./test_split_lock_iso
+
+- LLC & Memory Bandwidth Isolation
+
+    g++ test_mem_contention_iso.cpp -o test_mem_contention_iso && sudo ./test_mem_contention_iso
+
+- Power isolation
+
+    g++ test_power_iso.cpp -o test_power_iso && sudo ./test_power_iso
+
+
+## License
+
+[MIT](/LICENCE)
+
+## Contributors
+
+	Shuai Xue <[email protected]>
+	Shang Zhao <[email protected]>
+	Quan Chen <[email protected]>
+	Yihao Wu <[email protected]>
+	Shanpei Chen <[email protected]>
+	Yu Xu <[email protected]>
+	Zhen Ren <[email protected]>

bench.h

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+#ifndef BENCH_H
+#define BENCH_H
+
+#include <sys/time.h>
+typedef unsigned long long timestamp_t;
+
+static timestamp_t get_timestamp ()
+{
+    struct timeval now;
+    gettimeofday (&now, NULL);
+    return now.tv_usec + (timestamp_t)now.tv_sec * 1000000;
+
+}
+// return (now.tv_usec + (timestamp_t)now.tv_sec * 1000000) / 1000000.0;
+
+// ...
+// timestamp_t t0 = get_timestamp();
+// // Process
+// timestamp_t t1 = get_timestamp();
+
+// double secs = (t1 - t0) / 1000000.0L;
+
+#endif

cpuid.h

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+#ifndef CPUID_H
+#define CPUID_H
+
+#ifdef _WIN32
+#include <limits.h>
+#include <intrin.h>
+typedef unsigned __int32  uint32_t;
+
+#else
+#include <stdint.h>
+#endif
+
+
+class CPUID {
+
+public:
+  // explicit CPUID(unsigned level) {
+  //   asm volatile
+  //     ("cpuid" : "=a" (regs[0]), "=b" (regs[1]), "=c" (regs[2]), "=d" (regs[3])
+  //      : "0" (level));
+  // }
+  static uint32_t cpuid(unsigned level, int idx)
+  {
+    uint32_t regs[4];
+    asm volatile
+      ("cpuid" : "=a" (regs[0]), "=b" (regs[1]), "=c" (regs[2]), "=d" (regs[3])
+       : "0" (level));
+    return regs[idx];
+  }
+
+  static uint32_t cpuid_count(unsigned level, unsigned count, int idx) {
+    uint32_t regs[4];
+    asm volatile
+      ("cpuid" : "=a" (regs[0]), "=b" (regs[1]), "=c" (regs[2]), "=d" (regs[3])
+       : "0" (level), "2" (count));
+    return regs[idx];
+  }
+};
+
+
+// class CPUCount {
+//   uint32_t regs[4];
+
+// public:
+//   explicit CPUCount(unsigned level, unsigned count) {
+//     asm volatile
+//       ("cpuid" : "=a" (regs[0]), "=b" (regs[1]), "=c" (regs[2]), "=d" (regs[3])
+//        : "0" (level), "2" (count));
+//   }
+
+//   const uint32_t &EAX() const {return regs[0];}
+//   const uint32_t &EBX() const {return regs[1];}
+//   const uint32_t &ECX() const {return regs[2];}
+//   const uint32_t &EDX() const {return regs[3];}
+// };
+#endif // CPUID_H

duty_cycle.h

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+#ifndef DUTY_CYCLE_H
+#define DUTY_CYCLE_H
+
+#include "utility.h"
+
+// IA32_CLOCK_MODULATION
+#define MSR 0x19a
+#define enable_bit 4
+uint32_t duty_bit;
+uint32_t max_duty;
+
+int read_duty_cycle(int cpu)
+{
+    unsigned long long val = read_msr(cpu, MSR);
+    uint64_t enable = (val >> enable_bit);
+    uint64_t target = (val & (~(enable << enable_bit)));
+    //return enable, target
+    return target;
+}
+
+void write_duty_cycle(int cpu, int target)
+{
+    int enable = 0;
+    if (target > 0)
+        enable = 1;
+    else
+        enable = 0;
+    uint64_t val = (enable << enable_bit) | (target << duty_bit);
+    write_msr(cpu, MSR, val);
+}
+
+int duty_account(int duty)
+{
+    if (duty == 0)
+        return max_duty + 1;
+    else
+        return duty;
+}
+
+void init_cpu_duty_cycle()
+{
+    for (int cpu = 0; cpu < nr_cpus; cpu++)
+    {
+        write_duty_cycle(cpu, 0);
+    }
+}
+
+class DutyCycleScheme
+{
+public:
+    int min_duty;
+    // cpu => duty
+    map<int, int> duty;
+    map<int, double> duty_map;
+    vector<double> duty_rate = vector<double>(nr_cpus, 0);
+
+    void set_min_duty(int min_duty)
+    {
+        this->min_duty = min_duty;
+    }
+
+    DutyCycleScheme()
+    {
+        this->min_duty = 1;
+        for (auto it = core_vote_cpu.begin(); it != core_vote_cpu.end(); it++)
+        {
+            duty[it->second] = 0;
+        }
+        for (int duty = 0; duty < (int)max_duty + 1; duty++)
+        {
+            duty_map[duty] = duty_account(duty) * 100.0 / (max_duty + 1);
+        }
+    };
+
+    void update_duty(int cpu, int value, bool relative)
+    {
+        //We simply ignore those higher HT
+
+        if (!this->duty.count(cpu))
+            return;
+
+        if (relative)
+            value += duty_account(this->duty[cpu]);
+        else
+            value = duty_account(value);
+
+        if (value < this->min_duty)
+            value = this->min_duty;
+        if (value > (int)max_duty)
+            value = 0;
+
+        this->duty[cpu] = value;
+
+        write_duty_cycle(cpu, value);
+        this->duty_rate[cpu] = this->duty_map[value];
+        DEBUG_LOG("update cpu %d, value %d", cpu, value);
+        // cout << this->duty_rate[cpu] << endl;
+    }
+
+    //return duty rate for each cpu
+    vector<double> get_freq_rate()
+    {
+        return this->duty_rate;
+    }
+
+    bool get_thrtl_flag()
+    {
+        for (auto it = socket_vote_core.begin(); it != socket_vote_core.end(); it++)
+        {
+            for (auto itset = it->second.begin(); itset != it->second.end(); ++itset)
+            {
+                if (this->duty[*itset] > 0)
+                    return true;
+            }
+        }
+        return false;
+    }
+};
+
+DutyCycleScheme split_lock_scheme;
+
+#endif

init.h

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+#ifndef INIT_H
+#define INIT_H
+
+#include "duty_cycle.h"
+#include "utility.h"
+#include "cpuid.h"
+#include "intel_rdt.h"
+#include "mem_contention_iso.h"
+#include "vm_status.h"
+#include "rdt_manager.h"
+
+void init()
+{
+    init_topology();
+    nr_sockets = socket_topo.size();
+    nr_cpus = topo_cpu.size();
+
+    get_vm_topo();
+    nr_vms = vm_cpu.size();
+
+    uint32_t extension = CPUID::cpuid(0x6, 0) & 0x20;
+    if (extension)
+    {
+        duty_bit = 0x0;
+        max_duty = 15;
+    }
+    else
+    {
+        duty_bit = 0x1;
+        max_duty = 7;
+    }
+
+    rdtmon = RdtMonitoring();
+    rdtcat = RdtCAT();
+    rdtmba = RdtMBA();
+    rdtmgr = RdtManager();
+}
+#endif