Update S10 and P-tile models based on RX completion buffer size test …

…results Signed-off-by: Alex Forencich <[email protected]>
alexforencich · Jun 22, 2023 · c5d5405 · c5d5405
1 parent d2a20a0
commit c5d5405
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Showing 2 changed files with 5 additions and 1 deletion.
diff --git a/cocotbext/pcie/intel/ptile/ptile_model.py b/cocotbext/pcie/intel/ptile/ptile_model.py
@@ -331,6 +331,8 @@ def __init__(self,
         self.rx_queue = Queue()
 
         if port_num == 0:
+            # UG lists 1144 CPLH and 1444 "256 bit" CPLD
+            # Tests confirm >=1024 CPLH and >=2888 CPLD
             self.rx_buf_cplh_fc_limit = 1144
             self.rx_buf_cpld_fc_limit = 1444 * 2
         elif port_num == 1:

diff --git a/cocotbext/pcie/intel/s10/s10_model.py b/cocotbext/pcie/intel/s10/s10_model.py
@@ -255,8 +255,10 @@ def __init__(self,
 
         self.rx_queue = Queue()
 
+        # UG lists 770 CPLH and 2500 CPLD
+        # Tests confirm ~770 CPLH and ~2432 CPLD
         self.rx_buf_cplh_fc_limit = 770
-        self.rx_buf_cpld_fc_limit = 2500
+        self.rx_buf_cpld_fc_limit = 2432
         self.rx_buf_cplh_fc_count = 0
         self.rx_buf_cpld_fc_count = 0