GitHub - alexanderrotariu/aeu-vhdl-model: an arithmetic execution unit, modeled in VHDL using IPCatalog and userIPs. supports 8 bit addition, subtraction, multiplication and division

alexanderrotariu / aeu-vhdl-model Public

an arithmetic execution unit, modeled in VHDL using IPCatalog and userIPs. supports 8 bit addition, subtraction, multiplication and division

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Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
DE3.bd		DE3.bd
DE3.vhd		DE3.vhd
DE3.xpr		DE3.xpr
DE3.zip		DE3.zip
DE3_wrapper.vhd		DE3_wrapper.vhd
divider.xpr		divider.xpr
divider.zip		divider.zip
opMux.xpr		opMux.xpr
opMux.zip		opMux.zip

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an arithmetic execution unit, modeled in VHDL using IPCatalog and userIPs. supports 8 bit addition, subtraction, multiplication and division

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