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Errata 756 and 758: UART Condition (ARM-software#367)
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-In BSA The UART rule is relaxed based on particular UART
-IN Sbsa A new rule is added S_l3PER_01 for UART without relax


Change-Id: I3250ffef41e35894c8c83122eb822b9645197683

Signed-off-by: Ajayswar S <[email protected]>
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ajayswar-s authored Oct 24, 2024
1 parent 9b03cc3 commit e55a6dc
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Showing 3 changed files with 27 additions and 13 deletions.
4 changes: 2 additions & 2 deletions docs/arm_bsa_testcase_checklist.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -132,13 +132,13 @@ The below table provides the following details
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|602 |Check SATA CTRL Interface |B_PER_03 |Yes |Yes |Yes |Yes |Yes |No |No |
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|603 |Check Arm BSA UART register offsets |B_PER_05 |Yes |Yes |Yes |Yes |Yes |No |No |
|603 |Check Arm BSA UART register offsets |B_PER_05, S_L3PER_01 |Yes |Yes |Yes |Yes |Yes |No |No |
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|604 |Check Arm GENERIC UART Interrupt |B_PER_06, B_PER_07 |Yes |Yes |Yes |Yes |Yes |No |No |
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|605 |Memory Attribute of DMA |B_PER_09, B_PER_10 |Yes |Yes |Yes |Yes# |Yes |Yes |No |
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|606 |16550 compatible UART |B_PER_05 |Yes |Yes |Yes |Yes |Yes |No |No |
|606 |16550 compatible UART |B_PER_05, S_L3PER_01 |Yes |Yes |Yes |Yes |Yes |No |No |
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|701 |Non Secure Watchdog Access |B_WD_01, B_WD_02, S_L3WD_01 |Yes |Yes |Yes |Yes |Yes |No |No |
+-------+--------------------------------------------+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
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23 changes: 15 additions & 8 deletions test_pool/peripherals/operating_system/test_os_d003.c
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,8 @@
#include "val/common/sys_arch_src/gic/v3/gic_v3.h"

#define TEST_NUM (ACS_PER_TEST_NUM_BASE + 3)
#define TEST_RULE "B_PER_05"
#define TEST_RULE_BSA "B_PER_05"
#define TEST_RULE_SBSA "S_L3PER_01"
#define TEST_DESC "Check Arm BSA UART register offsets "
#define TEST_NUM1 (ACS_PER_TEST_NUM_BASE + 4)
#define TEST_RULE1 "B_PER_06, B_PER_07"
Expand Down Expand Up @@ -145,10 +146,13 @@ payload()
branch_to_test = &&exception_taken;
if (count == 0) {
val_print(ACS_PRINT_ERR, "\n No UART defined by Platform ", 0);
val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
if (g_build_sbsa)
val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
else
val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
return;
}
val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
val_set_status(index, RESULT_SKIP(TEST_NUM, 2));

while (count != 0) {
interface_type = val_peripheral_get_info(UART_INTERFACE_TYPE, count - 1);
Expand All @@ -158,7 +162,7 @@ payload()
{
l_uart_base = val_peripheral_get_info(UART_BASE0, count - 1);
if (l_uart_base == 0) {
val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
return;
}

Expand Down Expand Up @@ -189,10 +193,10 @@ payload1()

if (count == 0) {
val_print(ACS_PRINT_ERR, "\n No UART defined by Platform ", 0);
val_set_status(index, RESULT_FAIL(TEST_NUM1, 1));
val_set_status(index, RESULT_SKIP(TEST_NUM1, 1));
return;
}
val_set_status(index, RESULT_SKIP(TEST_NUM1, 1));
val_set_status(index, RESULT_SKIP(TEST_NUM1, 2));
while (count != 0) {
timeout = TIMEOUT_MEDIUM;
int_id = val_peripheral_get_info(UART_GSIV, count - 1);
Expand Down Expand Up @@ -236,7 +240,7 @@ payload1()
test_fail++;
}
} else {
val_set_status(index, RESULT_SKIP(TEST_NUM1, 2));
val_set_status(index, RESULT_SKIP(TEST_NUM1, 3));
}
}
count--;
Expand Down Expand Up @@ -268,7 +272,10 @@ os_d003_entry(uint32_t num_pe)
val_run_test_payload(TEST_NUM, num_pe, payload, 0);

/* get the result from all PE and check for failure */
status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
if (g_build_sbsa)
status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE_SBSA);
else
status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE_BSA);

val_report_status(0, ACS_END(TEST_NUM), NULL);

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13 changes: 10 additions & 3 deletions test_pool/peripherals/operating_system/test_os_d005.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,8 @@
#include "val/common/include/acs_pcie.h"

#define TEST_NUM (ACS_PER_TEST_NUM_BASE + 6)
#define TEST_RULE "B_PER_05"
#define TEST_RULE_BSA "B_PER_05"
#define TEST_RULE_SBSA "S_L3PER_01"
#define TEST_DESC "16550 compatible UART "

static
Expand Down Expand Up @@ -81,7 +82,10 @@ payload()

if (count == 0) {
val_print(ACS_PRINT_ERR, "\n No UART defined by Platform ", 0);
val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
if (g_build_sbsa)
val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
else
val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
return;
}

Expand Down Expand Up @@ -217,7 +221,10 @@ os_d005_entry(uint32_t num_pe)
val_run_test_payload(TEST_NUM, num_pe, payload, 0);

/* get the result from all PE and check for failure */
status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
if (g_build_sbsa)
status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE_SBSA);
else
status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE_BSA);

val_report_status(0, ACS_END(TEST_NUM), NULL);

Expand Down

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