feat: add reduce 1's fsm

Reduce_1s_FSM/reduce1s.sv

@@ -0,0 +1,62 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 19.10.2024 02:17:58
+// Design Name: 
+// Module Name: reduce1s
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module reduce1s(input logic clk,
+    input logic reset,
+    input logic in,
+    output logic [2:0] out);
+      typedef enum logic [2:0] {
+          S0 = 3'b000,
+          S1 = 3'b001,
+          S2 = 3'b010,
+          S3 = 3'b011,
+          S4 = 3'b100,
+          S5 = 3'b101,
+          S6 = 3'b110,
+          S7 = 3'b111
+      } state_t;
+
+      state_t current_state, next_state;
+
+      always_ff @(posedge clk or posedge reset) begin
+          if (reset)
+              current_state <= S0;
+          else
+              current_state <= next_state;
+      end
+
+      always_comb begin
+          next_state = current_state;
+          case (current_state)
+              S0: next_state = in ? S1 : S0;
+              S1: next_state = in ? S2 : S1;
+              S2: next_state = in ? S3 : S2;
+              S3: next_state = in ? S4 : S3;
+              S4: next_state = in ? S5 : S4;
+              S5: next_state = in ? S6 : S5;
+              S6: next_state = in ? S7 : S6;
+              S7: next_state = S7;
+          endcase
+      end
+
+      assign out = current_state;
+endmodule

Reduce_1s_FSM/reduce1s_tb.sv

@@ -0,0 +1,76 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 19.10.2024 02:50:04
+// Design Name: 
+// Module Name: reduce1s_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module reduce_ones_fsm_tb;
+
+    logic clk;
+    logic reset;
+    logic in;
+    logic [2:0] out;
+
+    reduce1s dut(clk, reset, in, out);
+
+
+    always #5 clk = ~clk;
+
+
+    initial begin
+
+        clk = 0;
+        reset = 1;
+        in = 0;
+
+        #10;
+        reset = 0;
+
+
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 0;
+
+
+        #20 in = 1;
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 1;
+        #10 in = 0;
+
+
+        #20 in = 1;
+        #10 in = 0;
+        #10 in = 1;
+        #10 in = 0;
+        #10 in = 1;
+        #10 in = 0;
+
+        #20 $finish;
+    end
+
+
+endmodule