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FPGA implementation via VHDL and Python simultation for a low-pass FIR Filter. Testbenches before the implmentation are also available.

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ZiliottoFilippoDev/FIR-Filter-VHDL-Implementation

 
 

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Designing of a low-Pass FIR filter both in VHDL and python to compare the results by a frequence analysis. The low-Pass FIR filter chose has 4 “taps” behavior in the frequency domain. The whole project was first testebenched via GTKwave software and then implemented with VHDL in a real FPGA.

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GTKWave Testbench alt text Response Signal FPGA alt text

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FPGA implementation via VHDL and Python simultation for a low-pass FIR Filter. Testbenches before the implmentation are also available.

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  • Jupyter Notebook 87.1%
  • Tcl 7.3%
  • VHDL 4.8%
  • Other 0.8%