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Expand Up @@ -12,7 +12,7 @@ and typical applications:</p>
<li>Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
<li>Built-in formal methods for checking properties and equivalence
<li>Mapping to ASIC standard cell libraries (in Liberty File Format)
<li>Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
<li>Mapping to Xilinx 7-Series and Lattice iCE40 and ECP5 FPGAs
<li>Foundation and/or front-end for custom flows
</ul>

Expand All @@ -21,6 +21,11 @@ the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the Yosys C++
code base.</p>

<p>Yosys also serves as backend for several tools that use formal methods to
reason about designs, such as <a href="https://yosyshq.readthedocs.io/en/latest/tools.html#formal-assertions-based-verification-abv-with-symbiyosys-sby">sby</a>
for SMT-solver-based formal property checking or <a href="https://yosyshq.readthedocs.io/en/latest/tools.html#mutation-coverage-with-yosys-mcy">mcy</a>
for evaluating the quality of testbenches with mutation coverage metrics.<p>

<p>Yosys is free software licensed under the <a
href="http://en.wikipedia.org/wiki/ISC_license">ISC license</a> (a GPL
compatible license that is similar in terms to the MIT license or the
Expand All @@ -34,7 +39,7 @@ the verilog file <tt>mydesign.v</tt>, synthesizes it to a gate-level netlist
using the cell library in the Liberty file <tt>mycells.lib</tt> and writes the
synthesized results as Verilog netlist to <tt>synth.v</tt>:</p>

<pre># read design
<pre># read design
read_verilog mydesign.v

# elaborate design hierarchy
Expand All @@ -61,7 +66,7 @@ write_verilog synth.v</pre>
<p>The <tt>synth</tt> command provides a good default script that can be used
as basis for simple synthesis scripts:</p>

<pre># read design
<pre># read design
read_verilog mydesign.v

# generic synthesis
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36 changes: 21 additions & 15 deletions documentation.in
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<h1>Documentation</h1>

<p>This page has links to all the documentaton resources
available for Yosys.</p>
<p>This page has links to some documentaton resources available for Yosys.</p>

<h2>Yosys Manual</h2>

<p>A quick first-steps tutorial can be found in the <a
href="https://github.com/YosysHQ/yosys/blob/master/README.md">README file</a>.</p>
href="https://github.com/YosysHQ/yosys/blob/master/README.md#getting-started">README file</a>.</p>

<p>The Yosys manual can be downloaded <a href="https://github.com/YosysHQ/yosys-manual-build/releases/download/manual/manual.pdf">here</a> (PDF).</p>

<p>The <a href="https://yosyshq.readthedocs.io/en/latest/">YosysHQ ReadTheDocs</a> has links to many resources for Yosys and Yosys-based tools.</p>

<h2>Support</h2>

The best places to ask questions are the <a
Expand All @@ -23,39 +24,44 @@ href="https://github.com/YosysHQ/yosys/issues/new">GitHub</a>.

<h2>Presentation Slides</h2>

<p><a href="https://github.com/YosysHQ/yosys-manual-build/releases/download/manual/presentation.pdf">This presentation slides</a> cover a wide range of topics related to Yosys. (The LaTeX source is part of the Yosys source distribution. Fell free to adapt the slides as needed.)</p>
<p><a href="https://github.com/YosysHQ/yosys-manual-build/releases/download/manual/presentation.pdf">This presentation slides</a> cover a wide range of topics related to Yosys. (The LaTeX source is part of the Yosys source distribution. Feel free to adapt the slides as needed.)</p>

<h2>Application Notes</h2>

<ul class="list">
<li><a href="files/yosys_appnote_010_verilog_to_blif.pdf">Yosys AppNote 010<a>: Converting Verilog to BLIF</li>
<li><a href="files/yosys_appnote_011_design_investigation.pdf">Yosys AppNote 011<a>: Interactive Design Investigation</li>
<li><a href="files/yosys_appnote_012_verilog_to_btor.pdf">Yosys AppNote 012<a>: Converting Verilog to BTOR</li>
<li><a href="files/yosys_appnote_010_verilog_to_blif.pdf">Yosys AppNote 010<a>: Converting Verilog to BLIF
<li><a href="files/yosys_appnote_011_design_investigation.pdf">Yosys AppNote 011<a>: Interactive Design Investigation
<li><a href="files/yosys_appnote_012_verilog_to_btor.pdf">Yosys AppNote 012<a>: Converting Verilog to BTOR
</ul>

<h2>Papers and other Publications</h2>

<p><i>This section is under construction.</i></p>
<p>Yosys is used in many academic projects. Below are a few papers from the
authors of Yosys. If you would like to use Yosys in your research or teaching,
but you need VHDL features not implemented in the open source frontend such as
VHDL or SystemVerilog Assertion support, <a href="https://www.yosyshq.com/contact">contact YosysHQ</a>
for an academic license!</p>

<ul class="list"><li>
Clifford Wolf, Johann Glaser. Yosys - A Free Verilog Synthesis Suite.
<ul class="list">
<li>C. Wolf, J. Glaser. Yosys - A Free Verilog Synthesis Suite.
In <i>Proceedings of Austrochip 2013</i>.
[<a href="files/yosys-austrochip2013.pdf">download pdf</a>]
</li><li>
Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect
<li>J. Glaser and C. Wolf. Methodology and Example-Driven Interconnect
Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable
Architectures. In Jan Haase, editor, <i>Models, Methods, and Tools for
Complex Chip Design. Lecture Notes in Electrical Engineering. Volume 265,
2014, pp 201-221. Springer, 2013.</i>
[<a href="files/intersynth-yosys-springer2013.pdf">download pdf</a>]
</li></ul>
<li>D. Shah, E. Hung, C. Wolf, S. Bazanski, D. Gisselquist, and M. Milanovic. Yosys + nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs. In <i>2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2019.</i>
[<a href="https://arxiv.org/abs/1903.10407">arXiv</a>]
</ul>

In papers and reports, please refer to Yosys as follows: <b>Clifford Wolf.
In papers and reports, please refer to Yosys as follows: <b>Claire Wolf.
Yosys Open SYnthesis Suite. https://yosyshq.net/yosys/</b>, e.g. using the
following BibTeX code:

<pre class="small">@MISC{Yosys,
author = {Clifford Wolf},
author = {Claire Wolf},
title = {Yosys Open SYnthesis Suite},
howpublished = "\url{https://yosyshq.net/yosys/}"
}</pre>
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Expand Up @@ -2,35 +2,31 @@

<h1>Download / Install</h1>

<p><b>Note:</b> At the moment Yosys is mostly tested on Linux. Expect some
difficulties when building on other platforms.</p>
<p>Download the latest Yosys release source code from GitHub:

<p>Download the Yosys 0.9 release source code from GitHub:</p>
<a href="https://github.com/YosysHQ/yosys/releases/latest">Release Notes and Download Links</a></p>

<ul>
<li><a href="https://github.com/YosysHQ/yosys/releases/tag/yosys-0.9">Release Notes</a></li>
<li><a href="https://github.com/YosysHQ/yosys/archive/yosys-0.9.zip">yosys-0.9.zip</a></li>
<li><a href="https://github.com/YosysHQ/yosys/archive/yosys-0.9.tar.gz">yosys-0.9.tar.gz</a></li>
</ul>
<p>Yosys is part of the <a href="https://www.yosyshq.com/tabby-cad-datasheet">Tabby CAD Suite</a> and the <a href="https://github.com/YosysHQ/oss-cad-suite-build">OSS CAD Suite</a>! The easiest way to use Yosys is to install the binary software suite, which contains all required dependencies and related tools. Download the latest binary release here: <a href="https://github.com/YosysHQ/oss-cad-suite-build/releases/latest">OSS CAD Suite Download Links</a></p>

<h2>Installing on Ubuntu</h2>
<p>Many Linux distributions also maintain Yosys packages (may or may not be up to date with the latest releases). Check your package manager!</p>

<a href="https://launchpad.net/~saltmakrell">Ruben Undheim</a> maintains a PPA
with Yosys Ubuntu packages. Use the following commands to install pre-compiled
Yosys binaries on Ubuntu:
<h2>Installing Tabby/OSS CAD Suite</h2>

<pre>sudo add-apt-repository ppa:saltmakrell/ppa
sudo apt-get update
sudo apt-get install yosys</pre>
<p>Binaries are available for Linux (x64, arm, arm64, riscv64), macOS (x64) and Windows (x64). Extract the archive in a location of your choice and source the environment script:</p>

His PPA only provides updated packages for the latest
Ubuntu desktop LTS version - trusty (14.04 LTS). As of vivid (15.04), yosys
will be available in the standard package repository for Ubuntu.
<ul>
<li>Linux/macOS:
<pre>source <extracted_location>/oss-cad-suite/environment</pre>
<li>Windows:
<pre><extracted_location>\oss-cad-suite\environment.bat</pre> (from existing shell)

<pre><extracted_location>\oss-cad-suite\start.bat</pre> (to create a new shell window)
</ul>

<h2>Yosys on MS Windows</h2>

There are two versions of Yosys for Win32. First there is the "official binary release"
of Yosys for Win32 which is cross-compiled using <a href="http://mxe.cc/">MXE</a>:
<p>There are two versions of Yosys for Win32. First there is the "official binary release"
of Yosys for Win32 which is cross-compiled using <a href="http://mxe.cc/">MXE</a>:</p>

<ul><li><a href="nogit/win32/yosys-win32-mxebin-0.9.zip">yosys-win32-mxebin-0.9.zip</a></ul>

Expand All @@ -41,7 +37,9 @@ Yosys C++ development on Windows:

<h2>Building Development Sources</h2>

Clone source code from GIT repository:
<h3>Linux / macOS</h3>

Clone source code from git repository:

<pre>git clone https://github.com/YosysHQ/yosys.git</pre>

Expand All @@ -61,4 +59,22 @@ See the <a
href="https://github.com/YosysHQ/yosys/blob/master/README.md">README</a> file
for detailed build instructions.

<h3>Windows</h3>

Builds for Windows can be built with VisualStudio or cross-compiled with <a href="http://mxe.cc/">MXE</a>.

VisualStudio project files are created as part of the automated tests on GitHub.
An easy way to compile Yosys on Windows is to use the project file from the
latest run:

<ul>
<li>Go to <a href="https://github.com/YosysHQ/yosys/actions/workflows/vs.yml?query=branch%3Amaster">the Visual Studio Build Action on GitHub</a>
<li>Click on the most recent completed run
<li>In Artifacts region find vcxsrc and click on it to download
<li>Unpack downloaded ZIP file
<li>Open YosysVS.sln with Visual Studio
</ul>

Detailed Windows build instructions can be found in the <a href="https://github.com/YosysHQ/yosys/blob/master/guidelines/Windows">guidelines</a>.

@footer@
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Expand Up @@ -33,15 +33,18 @@ information necessary to easily and quickly reproduce the problem you are seeing
<h2>2. What synthesis targets are supported by Yosys?</h2>

<p>Yosys is retargetable and adding support for additional targets is not very
hard. At the moment, Yosys ships with support for ASIC synthesis (from liberty
cell library files), iCE40 FPGAs, Xilinx 7-Series FPGAs, Silego GreenPAK4 devices,
and Gowinsemi GW1N/GW2A FPGAs.</p>
hard. At the moment, Yosys ships with mature flows targeting Lattice iCE40 and
ECP5 FPGAs as well as Xilinx 7-Series FPGAs, experimental flows for many others,
and support for ASIC synthesis from liberty cell library files.</p>

<p>Note that in all this cases Yosys only performs synthesis. For a complete
open source ASIC flow using Yosys see <a href="http://opencircuitdesign.com/qflow/">Qflow</a>,
<p>Note that in all these cases Yosys only performs synthesis. Yosys's sister
project <a href="https://github.com/YosysHQ/nextpnr">nextpnr</a> can be used for
place and route for several FPGA families.</p>

<p>For a complete open source ASIC flow using Yosys see <a href="http://opencircuitdesign.com/qflow/">Qflow</a>
or <a href="https://github.com/The-OpenROAD-Project/OpenLane">the OpenROAD Project's OpenLane</a>,
for a complete open source iCE40 flow see <a
href="http://www.clifford.at/icestorm/">Project IceStorm</a>. Yosys
Xilinx 7-Series synthesis output can be placed and routed with Xilinx Vivado.</p>
href="https://github.com/YosysHQ/icestorm">Project IceStorm</a>.</p>

<h2>3. Does Yosys support timing driven synthesis?</h2>

Expand All @@ -63,10 +66,6 @@ simply map arithmetic operations in the design to e.g. full-adder cells. See
e.g. inference of <tt>SB_CARRY+SB_LUT</tt> blocks for arithmetic operations in
the iCE40 flow.</p>

<p>There is limited support for FFs with non-inverted and inverted outputs in
Yosys and there are plans to further improve support for this cells in the near
future.</p>

<h2>5. The Verilog front-end does not create nice errors for invalid code!</h2>

<p>Not really a question, but yes, this is correct. The focus so far for
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This page contains links to other projects.

<h2>Related Projects</h2>

<p>These tools are built by members of the Yosys devteam.</p>

<ul>
<li><a href="https://github.com/amaranth-lang">Amaranth HDL</a> -- A Python embedded DSL for hardware description that emits Yosys RTLIL
<li><a href="https://github.com/YosysHQ/sby">sby</a> -- a front-end driver program for Yosys-based formal hardware verification flows
<li><a href="https://github.com/YosysHQ/mcy">mcy</a> -- Mutation Cover with Yosys
<li><a href="https://github.com/YosysHQ/nextpnr">nextpnr</a> -- A portable FPGA place and route tool
<li><a href="https://github.com/YosysHQ/icestorm">Project IceStorm</a> -- Documenting the Lattice iCE40 FPGAs Bitstream format
<li><a href="https://github.com/YosysHQ/prjtrellis">Project Trellis</a> -- Documenting the Lattice ECP5 Bitstream format
<li><a href="https://github.com/gatecat/prjoxide">Project Oxide</a> -- Documenting Lattice's 28nm FPGA parts
<li><a href=""></a>
</ul>

<h2>Online Services</h2>

<ul>
Expand All @@ -16,6 +31,7 @@ This page contains links to other projects.
<ul>
<li><a href="http://iverilog.icarus.com/">Icarus Verilog</a>
<li><a href="http://www.veripool.org/wiki/verilator">Verilator</a>
<li><a href="https://github.com/gtkwave/gtkwave">GTKWave waveform visualizer</a> -- use to view VCD files generated by the above tools
</ul>

<h2>Free Software for High-Level Circuit Synthesis and/or Analysis</h2>
Expand All @@ -25,7 +41,8 @@ This page contains links to other projects.
<li><a href="http://panda.dei.polimi.it/">PandA</a> -- high-level synthesis of C based descriptions
<li><a href="http://www.clash-lang.org">CLaSH</a> -- A compiler from Haskell to Verilog/VHDL
<li><a href="http://www.myhdl.org/">MyHDL</a> -- an open source Python package that lets you go from Python to silicon
<li><a href="http://milkymist.org/3/migen.html">Migen</a> -- a Python-based tool that aims at automating further the VLSI design process
<li><a href="https://m-labs.hk/gateware/migen/">Migen</a> -- a Python-based tool that aims at automating further the VLSI design process
<li><a href="https://github.com/enjoy-digital/litex">LiteX</a> -- Framework for rapidly assembling SoCs for use on FPGA
<li><a href="http://cx-lang.org/">Cx</a> -- A modern C-like language to create digital hardware
</ul>

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<!DOCTYPE html>
<html><head>
<title>Yosys Open SYnthesis Suite :: @@</title>
<link rel="stylesheet" href="stylesheet.css">
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