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This guide covers the main tools used in the open source FPGA development flow for Gowin FPGAs:

Tool Flow Overview

We have broad but not total coverage of supported primitives.

1. Yosys ‐ synth_gowin - Synthesis

   • Converts your Verilog code into a netlist of basic logic elements
   • Optimizes and maps designs to FPGA primitives
   • Outputs JSON format for place & route

2. Nextpnr‐Himbaechel Gowin - Place & Route

   • Places logic elements on the physical FPGA
   • Routes connections between elements
   • Ensures timing constraints are met
   • Takes JSON from Yosys and outputs placed design

3. gowin_pack - Bitstream Generation

   • Converts placed & routed design into binary bitstream
   • Handles device-specific configurations
   • Creates final .fs file for programming

4. openFPGALoader - Programming

   • Programs the bitstream onto the physical FPGA
   • Supports multiple programming interfaces
   • Handles device detection and configuration

Basic Flow Example

# 1. Synthesize Verilog to JSON netlist
yosys -p "read_verilog design.v; synth_gowin -json design.json"

# 2. Place and route the design
nextpnr-himbaechel --json design.json --write placed.json \
                   --device GW1NR-LV9QN88PC6/I5 \
                   --vopt cst=constraints.cst

# 3. Generate bitstream
gowin_pack -d GW1N-9C -o final.fs placed.json

# 4. Program the FPGA
openFPGALoader -b tangnano9k final.fs

Check the individual tool documentation for detailed options and advanced usage.

Transparency

Parts of this documentation were written with the help of AI, scripts, and scripts written by AI, but a human always had the final say.