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YashEkhande04/README.md

πŸ’« Hello Everyone!

🧠 Passionate about Electronics | ⚑ Custom ICs | πŸ› οΈ PCB Design | πŸ” RTL + VLSI

Hey there! I’m Yash Ekhande, a Final Year B.Tech student in Electronics & Computer Engineering at K.J. Somaiya College of Engineering, Mumbai. I specialize in building things that start from a datasheet and end on a real circuit board πŸ”Œ.

πŸ”¬ Interned @ FOSSEE, IIT Bombay
β€’ Designed and simulated 11 CMOS-based ICs using eSim (SPICE-based).
β€’ Created custom subcircuits (CD4078B, Schmitt Trigger, Op-Amps, etc.)
β€’ Built pulse-driven testbenches, waveform analysis, and symbol files.

πŸš€ What I Work On

  • CMOS Subcircuit Design & Simulation 🧩
  • RTL Design using Verilog (Car Parking System, Flip-Flops, ALUs) πŸ’»
  • PCB Design using Altium, KiCad πŸ“
  • Sensor-based Embedded Projects + Arduino + Automation 🌐
  • Analog + Digital IC Implementation in Cadence Virtuoso πŸ”§
  • eSim + Ngspice + Xschem Workflows πŸ“Š
  • Love for debugging hardware and soldering stuff! πŸ”πŸ”₯

πŸ† Highlights
β€’ Top 20 – National VLSI Hackathon (NIT Jamshedpur + VSD) 🏁
β€’ Successfully implemented Drowsiness Alert System, Smart Dispenser, and Parking IoT.
β€’ Mentoring juniors in circuit design and hands-on hardware projects πŸ’‘

🌟 I believe in building clean, functional, and scalable hardware systems β€” turning concepts into reality. Whether it’s designing a Schmitt Trigger or optimizing RTL logic, I’m here to make things blink, buzz, and solve problems.

πŸ“« [email protected]
πŸ”— LinkedIn | GitHub


🌐 Socials:

LinkedIn email


πŸ’» Tech Stack:

Arduino eSim Xschem LTspice KiCad Altium Designer Cadence Virtuoso Xilinx Vivado Eagle Verilog Festo Siemens TIA Portal


πŸ“Š GitHub Stats:




πŸ† GitHub Trophies:


πŸ” Top Contributed Repo:


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