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Releases: VHDL/PoC

v1.3.0

07 Apr 22:05
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New Features

  • Support more boards and devices in config package.
  • Added new helper functions.
  • Added new vector and record types.
  • Added new feature to select the RAM type for ocram_sdp.
  • Added new feature for selecting set_false_path or set_max_delay for synchronizers.
  • Added new feature for selecting registered output for synchronizers.

Braking Changes

  • Removed third party repositories (#5):
    • Modules: CoCoTb, UVVM, VUnit
    • Removed third party license texts.
    • Removed third party related documentation.

Changes

  • Changed use clauses from PoC.pkg to work.pkg.
  • Removed unused services:
    • Removed ReadTheDocs (#4)
    • Removed AppVeyor (#8)
    • Removed Travis-CI (#8)
    • Removed Landscape (#8)

Bug Fixes

  • Many bugfixes.
  • Fixed bug in cache_tagunit_seq when FA_CHUNKS = 1.
  • Fixed bug in sync_Bit_Xilinx not obeying to SYNC_DEPTH.

Documentation

  • Documentation is now licensed under CC-BY-4.0.
    A documentation license counter part to Apache License 2.0 for the code.
  • New documentation pipeline running on GitHub Actions (#7)
  • Reworked landing page
    • Updated shields.
  • Updated URLs to use github.com/VHDL/PoC
  • Fixed cross-references.
  • Updated link to OSVVM as well as license information of OSVVM (now Apache License 2.0 - like PoC).
  • Removed Xilinx ISE from documentation.
  • Added caution boxes to indicate potentially outdated documentation.
    This will be checked and updated in the upcoming v1.x releases.
  • Added PLC2 as a user of PoC.
  • Updated documentation to Sphinx v8.3
    • Removed sphinx_rtd_theme submodule.
    • Use latest sphinx_rtd_theme plus custom CSS enhancements.
    • Updated Sphinx extensions.
  • Added PoC logo and icon.

Tests

  • New verification pipeline using GHDL and OSVVM running on GitHub Actions
    #7

Related Issues and PullRequests

Contributors


Published from Verify PoC and Generate Documentation workflow triggered by @Paebbels on 2025-04-07 22:05:44 UTC.