rtlode-v2.2.0

Changelog:

• [NOTE] New more compact pipeline structure.

Full Changelog: v2.1.0...v2.2.0

rtlode-v2.1.0

Changelog:

• [NOTE] Upgraded to Intel Acceleration Stack 1.2.1. Updated ip cores to quartus 19.1.
• [NOTE] Added and improved a lot of test cases.
• [FIX] Some logic of the csr_handler did not convert into standard conform verilog.
• [FIX] Limited buffer access in runtime to actual buffer size.
• [FIX] Fixed two bugs in the host ram handler.
• [FIX] Fixed truncation warnings for fifo address logic.
• [FIX] Timing constraints are now properly applied to the build process.
• [FEATURE] Build process now creates an extra directory for each call. The generated solver verilog files is preserved in this build directory.
• [FEATURE] Added build information output in runtime.
• [FEATURE] Reworked priority encoder to simplify logic and remove a latch.
• [FEATURE] Simplified reset logic of hram handler to simplify timing conform routing.

rtlode-v2.0.1

Changelog:

• [FIX] Changed myhdl dependency to dev version. Stable version is currently too old.

rtlode-v2.0.0

Code freeze related to the publishing of article 10.1002/spe.3043.