Merge pull request #22 from YosysHQ/main

bump fork for version 0.43

.github/workflows/test-compile.yml

@@ -64,11 +64,11 @@ jobs:
           $CXX --version
 
       # minimum standard
-      - name: Build C++11
+      - name: Build C++17
         shell: bash
         run: |
           make config-$CC_SHORT
-          make -j$procs CXXSTD=c++11 compile-only
+          make -j$procs CXXSTD=c++17 compile-only
 
       # maximum standard, only on newest compilers
       - name: Build C++20

.github/workflows/test-verific.yml

@@ -39,6 +39,7 @@ jobs:
           echo "ENABLE_VERIFIC := 1" >> Makefile.conf
           echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf
           echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf
           echo "ENABLE_CCACHE := 1" >> Makefile.conf
           make -j${{ env.procs }}
 

CHANGELOG

@@ -2,9 +2,21 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.42 .. Yosys 0.43-dev
+Yosys 0.43 .. Yosys 0.44-dev
 --------------------------
 
+Yosys 0.42 .. Yosys 0.43
+--------------------------
+ * Various
+    - C++ compiler with C++17 support is required.
+    - Support for IO liberty files for verification.
+    - Limit padding from shiftadd for "peepopt" pass.
+
+ * Verific support
+    - Support building Yosys with various Verific library
+      configurations. Can be built now without YosysHQ 
+      specific patch and extension library.
+
 Yosys 0.41 .. Yosys 0.42
 --------------------------
  * New commands and options

Makefile

@@ -17,10 +17,12 @@ ENABLE_READLINE := 1
 ENABLE_EDITLINE := 0
 ENABLE_GHDL := 0
 ENABLE_VERIFIC := 0
+ENABLE_VERIFIC_SYSTEMVERILOG := 1
+ENABLE_VERIFIC_VHDL := 1
+ENABLE_VERIFIC_HIER_TREE := 1
+ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0
 ENABLE_VERIFIC_EDIF := 0
 ENABLE_VERIFIC_LIBERTY := 0
-DISABLE_VERIFIC_EXTENSIONS := 0
-DISABLE_VERIFIC_VHDL := 0
 ENABLE_COVER := 1
 ENABLE_LIBYOSYS := 0
 ENABLE_ZLIB := 1
@@ -90,7 +92,7 @@ all: top-all
 YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
 VPATH := $(YOSYS_SRC)
 
-CXXSTD ?= c++11
+CXXSTD ?= c++17
 CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
 LIBS := $(LIBS) -lstdc++ -lm
 PLUGIN_LINKFLAGS :=
@@ -141,7 +143,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.42+0
+YOSYS_VER := 0.43+0
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -157,7 +159,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9b6afcf.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline ead4718.. | wc -l`/;" Makefile
 
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
 
@@ -471,8 +473,24 @@ endif
 LIBS_VERIFIC =
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib
-VERIFIC_COMPONENTS ?= verilog database util containers hier_tree
-ifneq ($(DISABLE_VERIFIC_VHDL),1)
+VERIFIC_COMPONENTS ?= database util containers
+ifeq ($(ENABLE_VERIFIC_HIER_TREE),1)
+VERIFIC_COMPONENTS += hier_tree
+CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),)
+VERIFIC_COMPONENTS += hier_tree
+endif
+endif
+ifeq ($(ENABLE_VERIFIC_SYSTEMVERILOG),1)
+VERIFIC_COMPONENTS += verilog
+CXXFLAGS += -DVERIFIC_SYSTEMVERILOG_SUPPORT
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
+VERIFIC_COMPONENTS += verilog
+endif
+endif
+ifeq ($(ENABLE_VERIFIC_VHDL),1)
 VERIFIC_COMPONENTS += vhdl
 CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
 else
@@ -488,9 +506,13 @@ ifeq ($(ENABLE_VERIFIC_LIBERTY),1)
 VERIFIC_COMPONENTS += synlib
 CXXFLAGS += -DVERIFIC_LIBERTY_SUPPORT
 endif
-ifneq ($(DISABLE_VERIFIC_EXTENSIONS),1)
+ifeq ($(ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS),1)
 VERIFIC_COMPONENTS += extensions
 CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/extensions),)
+VERIFIC_COMPONENTS += extensions
+endif
 endif
 CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
 ifeq ($(OS), Darwin)
@@ -736,7 +758,7 @@ CXXFLAGS_NOVERIFIC = $(CXXFLAGS)
 LIBS_NOVERIFIC = $(LIBS)
 endif
 
-$(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in
+$(PROGRAM_PREFIX)yosys-config: misc/yosys-config.in $(YOSYS_SRC)/Makefile
 	$(P) $(SED) -e 's#@CXXFLAGS@#$(subst -Ilibs/dlfcn-win32,,$(subst -I. -I"$(YOSYS_SRC)",-I"$(DATDIR)/include",$(strip $(CXXFLAGS_NOVERIFIC))))#;' \
 			-e 's#@CXX@#$(strip $(CXX))#;' -e 's#@LINKFLAGS@#$(strip $(LINKFLAGS) $(PLUGIN_LINKFLAGS))#;' -e 's#@LIBS@#$(strip $(LIBS_NOVERIFIC) $(PLUGIN_LIBS))#;' \
 			-e 's#@BINDIR@#$(strip $(BINDIR))#;' -e 's#@DATDIR@#$(strip $(DATDIR))#;' < $< > $(PROGRAM_PREFIX)yosys-config
@@ -1015,7 +1037,7 @@ qtcreator:
 vcxsrc: $(GENFILES) $(EXTRA_TARGETS)
 	rm -rf yosys-win32-vcxsrc-$(YOSYS_VER){,.zip}
 	set -e; for f in `ls $(filter %.cc %.cpp,$(GENFILES)) $(addsuffix .cc,$(basename $(OBJS))) $(addsuffix .cpp,$(basename $(OBJS))) 2> /dev/null`; do \
-		echo "Analyse: $$f" >&2; cpp -std=c++11 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt
+		echo "Analyse: $$f" >&2; cpp -std=c++17 -MM -I. -D_YOSYS_ $$f; done | sed 's,.*:,,; s,//*,/,g; s,/[^/]*/\.\./,/,g; y, \\,\n\n,;' | grep '^[^/]' | sort -u | grep -v kernel/version_ > srcfiles.txt
 	bash misc/create_vcxsrc.sh yosys-win32-vcxsrc $(YOSYS_VER) $(GIT_REV)
 	echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys (Version Information Unavailable)\"; }" > kernel/version.cc
 	zip yosys-win32-vcxsrc-$(YOSYS_VER)/genfiles.zip $(GENFILES) kernel/version.cc

README.md

@@ -71,7 +71,7 @@ Many Linux distributions also provide Yosys binaries, some more up to date than
 Building from Source
 ====================
 
-You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
+You need a C++ compiler with C++17 support (up-to-date CLANG or GCC is
 recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
 TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
 Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.

backends/cxxrtl/cxxrtl_backend.cc

@@ -1138,7 +1138,7 @@ struct CxxrtlWorker {
 		f << indent << "// cell " << cell->name.str() << " syncs\n";
 		for (auto conn : cell->connections())
 			if (cell->output(conn.first))
-				if (is_cxxrtl_sync_port(cell, conn.first)) {
+				if (is_cxxrtl_sync_port(cell, conn.first) && !conn.second.empty()) {
 					f << indent;
 					dump_sigspec_lhs(conn.second, for_debug);
 					f << " = " << mangle(cell) << access << mangle_wire_name(conn.first) << ".curr;\n";

backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc

@@ -47,7 +47,7 @@ cxxrtl_handle cxxrtl_create_at(cxxrtl_toplevel design, const char *top_path_) {
 
 	cxxrtl_handle handle = new _cxxrtl_handle;
 	handle->module = std::move(design->module);
-	handle->module->debug_info(handle->objects, top_path);
+	handle->module->debug_info(&handle->objects, nullptr, top_path);
 	delete design;
 	return handle;
 }

backends/cxxrtl/runtime/cxxrtl/cxxrtl.h

@@ -1582,7 +1582,7 @@ struct module {
 
 	// Compatibility method.
 #if __has_attribute(deprecated)
-	__attribute__((deprecated("Use `debug_info(path, &items, /*scopes=*/nullptr);` instead. (`path` could be \"top \".)")))
+	__attribute__((deprecated("Use `debug_info(&items, /*scopes=*/nullptr, path);` instead.")))
 #endif
 	void debug_info(debug_items &items, std::string path) {
 		debug_info(&items, /*scopes=*/nullptr, path);

docs/source/conf.py

@@ -5,7 +5,7 @@
 project = 'YosysHQ Yosys'
 author = 'YosysHQ GmbH'
 copyright ='2024 YosysHQ GmbH'
-yosys_ver = "0.42"
+yosys_ver = "0.43"
 
 # select HTML theme
 html_theme = 'furo'

docs/source/getting_started/installation.rst

@@ -84,7 +84,7 @@ not regularly tested:
 Build prerequisites
 ^^^^^^^^^^^^^^^^^^^
 
-A C++ compiler with C++11 support is required as well as some standard tools
+A C++ compiler with C++17 support is required as well as some standard tools
 such as GNU Flex, GNU Bison, Make and Python.  Some additional tools: readline,
 libffi, Tcl and zlib; are optional but enabled by default (see
 :makevar:`ENABLE_*` settings in Makefile). Graphviz and Xdot are used by the

docs/source/getting_started/scripting_intro.rst

@@ -8,10 +8,40 @@ file format and how you can make your own synthesis scripts.
 Yosys script files typically use the :file:`.ys` extension and contain a set of
 commands for Yosys to run sequentially.  These commands are the same ones we
 were using on the previous page like :cmd:ref:`read_verilog` and
-:cmd:ref:`hierarchy`.  As with the interactive shell, each command consists of
-the command name, and an optional whitespace separated list of arguments.
-Commands are terminated with the newline character, or by a semicolon (;). Empty
-lines, and lines starting with the hash sign (#), are ignored.
+:cmd:ref:`hierarchy`.
+
+Script parsing
+~~~~~~~~~~~~~~
+
+As with the interactive shell, each command consists of the command name, and an
+optional whitespace separated list of arguments. Commands are terminated with
+the newline character, and anything after a hash sign ``#`` is a comment (i.e.
+it is ignored).
+
+It is also possible to terminate commands with a semicolon ``;``.  This is
+particularly useful in conjunction with the ``-p <command>`` command line
+option, where ``<command>`` can be a string with multiple commands separated by
+semicolon. In-line comments can also be made with the colon ``:``, where the end
+of the comment is a semicolon ``;`` or a new line.
+
+.. code-block::
+   :caption: Using the ``-p`` option
+
+   $ yosys -p "read_verilog fifo.v; :this is a comment; prep"
+
+.. warning::
+
+   The space after the semicolon is required for correct parsing. ``log a;log
+   b;`` for example will display ``a;log b`` instead of ``a`` and ``b`` as might
+   be expected.
+
+Another special character that can be used in Yosys scripts is the bang ``!``.
+Anything after the bang will be executed as a shell command.  This can only be
+terminated with a new line.  Any semicolons, hashes, or other special characters
+will be passed to the shell.  If an error code is returned from the shell it
+will be raised by Yosys.  :cmd:ref:`exec` provides a much more flexible way of
+executing commands, allowing the output to be logged and more control over when
+to generate errors.
 
 The synthesis starter script
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~

docs/source/yosys_internals/index.rst

@@ -25,7 +25,7 @@ wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
 
 .. _k68 CPU: http://opencores.org/projects/k68
 
-Yosys is written in C++, targeting C++11 at minimum. This chapter describes some
+Yosys is written in C++, targeting C++17 at minimum. This chapter describes some
 of the fundamental Yosys data structures. For the sake of simplicity the C++
 type names used in the Yosys implementation are used in this chapter, even
 though the chapter only explains the conceptual idea behind it and can be used

frontends/ast/ast.h

@@ -17,12 +17,7 @@
  *
  *  ---
  *
- *  This is the AST frontend library.
- *
- *  The AST frontend library is not a frontend on it's own but provides a
- *  generic abstract syntax tree (AST) abstraction for HDL code and can be
- *  used by HDL frontends. See "ast.h" for an overview of the API and the
- *  Verilog frontend for an usage example.
+ *  This is support code for the Verilog frontend at frontends/verilog
  *
  */
 

frontends/liberty/liberty.cc

@@ -214,6 +214,18 @@ static RTLIL::SigSpec parse_func_expr(RTLIL::Module *module, const char *expr)
 	return stack.back().sig;
 }
 
+static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func, const char *three_state_expr)
+{
+	RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
+
+	RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
+	cell->setParam(ID::WIDTH, GetSize(func));
+	cell->setPort(ID::A, func);
+	cell->setPort(ID::EN, create_inv_cell(module, three_state));
+	cell->setPort(ID::Y, module->addWire(NEW_ID));
+	return cell->getPort(ID::Y);
+}
+
 static void create_ff(RTLIL::Module *module, LibertyAst *node)
 {
 	RTLIL::SigSpec iq_sig(module->addWire(RTLIL::escape_id(node->args.at(0))));
@@ -695,18 +707,24 @@ struct LibertyFrontend : public Frontend {
 					LibertyAst *func = node->find("function");
 					if (func == NULL)
 					{
-						if (!flag_ignore_miss_func)
-						{
-							log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
-						} else {
-							log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
-							delete module;
-							goto skip_cell;
+						if (dir->value != "inout") { // allow inout with missing function, can be used for power pins
+							if (!flag_ignore_miss_func)
+							{
+								log_error("Missing function on output %s of cell %s.\n", log_id(wire->name), log_id(module->name));
+							} else {
+								log("Ignoring cell %s with missing function on output %s.\n", log_id(module->name), log_id(wire->name));
+								delete module;
+								goto skip_cell;
+							}
+						}
+					} else {
+						RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
+						LibertyAst *three_state = node->find("three_state");
+						if (three_state) {
+							out_sig = create_tristate(module, out_sig, three_state->value.c_str());
 						}
+						module->connect(RTLIL::SigSig(wire, out_sig));
 					}
-
-					RTLIL::SigSpec out_sig = parse_func_expr(module, func->value.c_str());
-					module->connect(RTLIL::SigSig(wire, out_sig));
 				}
 			}
 

frontends/verific/Makefile.inc

@@ -10,7 +10,7 @@ EXTRA_TARGETS += share/verific
 share/verific:
 	$(P) rm -rf share/verific.new
 	$(Q) mkdir -p share/verific.new
-ifneq ($(DISABLE_VERIFIC_VHDL),1)
+ifeq ($(ENABLE_VERIFIC_VHDL),1)
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008