synth: Save checkpoint without stdcells#3817
synth: Save checkpoint without stdcells#3817openroad-ci wants to merge 2 commits intoThe-OpenROAD-Project:masterfrom
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Between the canonicalization step and the rest of synthesis we store a .rtlil checkpoint. Make it smaller by stripping standard cell definitions from it. Signed-off-by: Martin Povišer <[email protected]>
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@oharboe take two, we'll see if any errors appear |
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@povik I suppose the difference in WNS is just the garden variety Yosys churn? |
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@oharboe I think so, yeah |
Signed-off-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
🤞 |
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@maliberty Thoughts? |
| # Strip away standard cell definitions to make the checkpoint smaller. | ||
| delete =A:\liberty_cell=1 |
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@povik you'll have a better idea than I do if this is a good change.
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I think it's fine even though it relies on undocumented yosys behavior. We can always go back
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Why does this change QOR? |
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I think the ball is in my court to resolve the conflict and add update of private metrics. I had a secure CI running but before I reacted to its results the public metrics went stale
The theory is internal yosys counters used for naming objects are influenced by the extra read_liberty command. This propagates to different iteration order and optimization results |
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merge? |
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It has conflicts so no |
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@povik Merge w/master and good to go? |
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You would need to rerun the designs not just merge. There are two other PRs with pending metrics updates that this will need to queue behind. |
4 participants
Between the canonicalization step and the rest of synthesis we store a .rtlil checkpoint. Make it smaller by stripping standard cell definitions from it.
Resolves #3815
Updated Rules
[WARNING] Multiple clocks not supported. Will use first clock: mrx_clk_pad_i: 300.0000.
[WARNING] Multiple clocks not supported. Will use first clock: mrx_clk_pad_i: 300.0000.
designs/asap7/jpeg_lvt/rules-base.json updates:
designs/asap7/mock-alu/rules-base.json updates:
[WARNING] Multiple clocks not supported. Will use first clock: clk: 333.0000.
designs/asap7/uart/rules-base.json updates:
designs/nangate45/bp_be_top/rules-base.json updates:
designs/nangate45/ibex/rules-base.json updates:
designs/nangate45/jpeg/rules-base.json updates:
[WARNING] Multiple clocks not supported. Will use first clock: clk_i: 3.0000.
designs/sky130hd/jpeg/rules-base.json updates:
[WARNING] Multiple clocks not supported. Will use first clock: ext_clk: 15.0000.
designs/sky130hd/microwatt/rules-base.json updates:
designs/sky130hs/ibex/rules-base.json updates:
designs/sky130hs/riscv32i/rules-base.json updates:
Messages from CI
[INFO] asap7/minimal not included in CI.
[INFO] gf12 not included in the update.
[INFO] gf55 not included in the update.
[INFO] nangate45/bp_quad not included in CI.
[INFO] rapidus2hp not included in the update.