Initial support for Verilog-style preprocessor#6

Draft

citorva wants to merge 4 commits intoSystemRDL:masterfrom citorva:master

+43-5

Commits on Aug 29, 2024

adding initial support for Verilog-style preprocessor
Venceslas Duet
committed
enabling Perl prepocessor
Venceslas Duet
committed
add a field for the perl code
Venceslas Duet
committed
Add inlined preprocessor defined content support
Venceslas Duet
committed