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Name		Name	Last commit message	Last commit date
Latest commit Ondrej Ille src: Deduplicate logic of read enable generation. May 4, 2024 3411923 · May 4, 2024 History 172 Commits
.github/workflows		.github/workflows	Update to use trusted deploy	Oct 29, 2023
docs		docs	Fix accidental blocking assignment in always_ff for read buffering st…	Jan 6, 2024
hdl-src		hdl-src	Add Intel Avalon MM cpuif. #40	May 15, 2023
src/peakrdl_regblock		src/peakrdl_regblock	src: Deduplicate logic of read enable generation.	May 4, 2024
tests		tests	Add packed struct overlay for external register bitfields. #84	Mar 30, 2024
.gitignore		.gitignore	Reorganize how tb infrstructure selects toolchains	Oct 22, 2023
.readthedocs.yaml		.readthedocs.yaml	Fix hwif type name generation to properly handle parameterized compon…	Oct 12, 2023
LICENSE		LICENSE	initial dev	Jun 2, 2021
MANIFEST.in		MANIFEST.in	Switch to use regular non-namespaced package	Jun 10, 2022
README.md		README.md	Add coveralls	Mar 14, 2023
pyproject.toml		pyproject.toml	Fix typo in pyproject keywords	Nov 8, 2023

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PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details