Name		Name	Last commit message	Last commit date
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magic		magic
verilog		verilog
.gitignore		.gitignore
README.md		README.md

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VLSI

All the projects and assignments done as part of VLSI course.

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All the projects and assignments done as part of VLSI course.

magic verilog vlsi wallace-tree-multiplier cmos vlsi-circuits recursive-doubling-cla ripple-carry-adder universal-shift-register

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