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RISC-V-ISA-32-bit-Assembler-and-Simulator

This was a group project of 5 for an academic course called Computer Architecture. The project is related to creating a simulator which will read codes written in RISC-V ISA and can simulate how it is processed in a system. This being one of my first large projects, was done without much documentation as I was not enough better at coding then. But still it adds into my experience being doing a large code and connect different functionalities.

The project was of 2 parts:

  1. To convert the RISC code into machine level opcodes and also store them into memory which is a text file for this project.
  2. To read the opcodes and process them as a pipeline would do and also print some statistics.

Each part has its own readme which briefly explain how everyone in the team divided the tasks and how to run the code.

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