[Glorious GMMK Full (2021)] Initial support for Glorious GMMK Full (2…

…021) 1. GMMK 2021 FULL with two SNLED2735 RGB chips by SPI Tuning 1. Tightly reduce stack size USE_EXCEPTIONS_STACKSIZE = 0xd0 USE_PROCESS_STACKSIZE = 0x200 3. -Os compile option and LTO_ENABLE=yes 4. Self-defined rand() for animations using rand() 6. Reduce idle thread stack size and disable registry in chconf.h Commit amended to match RGB controls in keymap and to clean up some things by Adam Honse <[email protected]>
SonixQMK · Sep 4, 2021 · 7148084 · 7148084
1 parent b368c4a
commit 7148084
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diff --git a/bin/build_all.py b/bin/build_all.py
@@ -1,7 +1,7 @@
 import subprocess
 import os
 
-BOARDS = ['redragon/k552/rev1', 'redragon/k552/rev2', 'redragon/k530', 'redragon/k556', 'redragon/k580', 'keychron/c1', 'keychron/k2', 'keychron/k3', 'keychron/k4', 'keychron/k6', 'keychron/k8', 'ajazz/ak33/rev1', 'ajazz/ak33/rev2', 'smartduck/xs61', 'spcgear/gk530', 'spcgear/gk540', 'sharkoon/sgk3', 'womier/k87', 'flashquark/horizon_z', 'ffc/ffc61']
+BOARDS = ['redragon/k552/rev1', 'redragon/k552/rev2', 'redragon/k530', 'redragon/k556', 'redragon/k580', 'keychron/c1', 'keychron/k2', 'keychron/k3', 'keychron/k4', 'keychron/k6', 'keychron/k8', 'ajazz/ak33/rev1', 'ajazz/ak33/rev2', 'smartduck/xs61', 'spcgear/gk530', 'spcgear/gk540', 'sharkoon/sgk3', 'womier/k87', 'flashquark/horizon_z', 'ffc/ffc61', 'glorious/gmmk_full']
 
 for kb in BOARDS:
     subprocess.run(f"bin/qmk compile -kb {kb} -km all -j{os.cpu_count()}", shell=True)
diff --git a/keyboards/glorious/gmmk_full/SPI.h b/keyboards/glorious/gmmk_full/SPI.h
@@ -0,0 +1,186 @@
+#ifndef __SN32F240_SSP_H
+#define __SN32F240_SSP_H
+
+
+/*_____ I N C L U D E S ____________________________________________________*/
+
+/*_____ D E F I N I T I O N S ______________________________________________*/
+/*
+Base Address: 0x4001 C000 (SSP0)
+							0x4005 8000 (SSP1)
+*/		
+
+/* SSP n Control register 0 <SSPn_CTRL0> (0x00) */
+#define	SSP_SSPEN_DIS 					0			//[0:0] SSP enable bit
+#define	SSP_SSPEN_EN  					1
+#define mskSSP_SSPEN_DIS				(SSP_SSPEN_DIS<<0)
+#define	mskSSP_SSPEN_EN 				(SSP_SSPEN_EN<<0)
+
+																			//[1:1] Loop back mode disable
+#define	SSP_LOOPBACK_DIS				0			//Disable
+#define	SSP_LOOPBACK_EN					1			//Data input from data output
+#define mskSSP_LOOPBACK_DIS			(SSP_LOOPBACK_DIS<<1)
+#define	mskSSP_LOOPBACK_EN 			(SSP_LOOPBACK_EN<<1)
+
+																			//[2:2] Slave data output disable bit (ONLY used in slave mode)
+#define	SSP_SDODIS_EN						0 		//Enable slave data output
+#define	SSP_SDODIS_DIS					1 		//Disable slave data output. (MISO=0)
+#define mskSSP_SDODIS_EN				(SSP_SDODIS_EN<<2)
+#define	mskSSP_SDODIS_DIS 			(SSP_SDODIS_DIS<<2)
+
+#define	SSP_MS_MASTER_MODE  		0			//[3:3] Master/Slave selection bit
+#define	SSP_MS_SLAVE_MODE  			1			
+#define mskSSP_MS_MASTER_MODE		(SSP_MS_MASTER_MODE<<3)
+#define	mskSSP_MS_SLAVE_MODE 		(SSP_MS_SLAVE_MODE<<3)
+
+#define	SSP_FORMAT_SPI_MODE  		0			//[4:4] Interface format
+#define	SSP_FORMAT_SSP_MODE  		1			
+#define mskSSP_FORMAT_SPI_MODE	(SSP_FORMAT_SPI_MODE<<4)
+#define	mskSSP_FORMAT_SSP_MODE 	(SSP_FORMAT_SSP_MODE<<4)
+
+																			//[7:6] SSP FSM and FIFO Reset bit
+#define	SSP_FRESET_DO_NOTHING		0			//Do nothing																	
+#define	SSP_FRESET_RESET_FIFO		3			//Reset finite state machine and FIFO
+#define mskSSP_FRESET_DO_NOTHING	(SSP_FRESET_DO_NOTHING<<6)
+#define	mskSSP_FRESET_RESET_FIFO 	(SSP_FRESET_RESET_FIFO<<6)
+
+#define	SSP_DL_3 								2			//[11:8] Data Length = DL[3:0]+1
+#define	SSP_DL_4 								3		
+#define	SSP_DL_5 								4		
+#define	SSP_DL_6 								5		
+#define	SSP_DL_7 								6		
+#define	SSP_DL_8 								7		
+#define	SSP_DL_9 								8	
+#define	SSP_DL_10 							9		
+#define	SSP_DL_11								10	
+#define	SSP_DL_12								11	
+#define	SSP_DL_13 							12	
+#define	SSP_DL_14 							13	
+#define	SSP_DL_15 							14	
+#define	SSP_DL_16 							15	
+
+#define	SSP_TXFIFOTH_0					0		//[14:12]TX FIFO Threshold level
+#define	SSP_TXFIFOTH_1					1		
+#define	SSP_TXFIFOTH_2					2		
+#define	SSP_TXFIFOTH_3					3		
+#define	SSP_TXFIFOTH_4					4		
+#define	SSP_TXFIFOTH_5					5		
+#define	SSP_TXFIFOTH_6					6		
+#define	SSP_TXFIFOTH_7					7		
+
+#define	SSP_RXFIFOTH_0					0		//[17:15]RX FIFO Threshold level
+#define	SSP_RXFIFOTH_1					1		
+#define	SSP_RXFIFOTH_2					2		
+#define	SSP_RXFIFOTH_3					3		
+#define	SSP_RXFIFOTH_4					4		
+#define	SSP_RXFIFOTH_5					5		
+#define	SSP_RXFIFOTH_6					6		
+#define	SSP_RXFIFOTH_7					7		
+
+																		//[18:18]Auto-SEL disable bit. For SPI mode only.
+#define	SSP_SELDIS_EN						0		//Enable Auto-SEL flow control
+#define	SSP_SELDIS_DIS					1		//Disable Auto-SEL flow control
+#define	mskSSP_SELDIS_EN 				(SSP_SELDIS_EN<<18)
+#define	mskSSP_SELDIS_DIS 			(SSP_SELDIS_DIS<<18)
+
+
+/* SSP n Control register 1 <SSPn_CTRL1> (0x04) */
+																		//[0:0]MSB/LSB selection bit
+#define	SSP_MLSB_MSB						0		//MSB transmit first
+#define	SSP_MLSB_LSB						1		//LSB transmit first
+#define	mskSSP_MLSB_MSB 				(SSP_MLSB_MSB<<0)
+#define	mskSSP_MLSB_LSB 				(SSP_MLSB_LSB<<0)
+
+																		//[1:1]Clock polarity selection bit
+#define	SSP_CPOL_SCK_IDLE_LOW		0		//SCK idles at Low level
+#define	SSP_CPOL_SCK_IDLE_HIGH	1		//SCK idles at High level
+#define	mskSSP_CPOL_SCK_IDLE_LOW 	(SSP_CPOL_SCK_IDLE_LOW<<1)
+#define	mskSSP_CPOL_SCK_IDLE_HIGH (SSP_CPOL_SCK_IDLE_HIGH<<1)
+
+																		//[2:2]Clock phase for edge sampling
+#define	SSP_CPHA_FALLING_EDGE		0		//Data changes at clock falling edge
+#define	SSP_CPHA_RISING_EDGE		1		//Data changes at clock rising edge
+#define	mskSSP_CPHA_FALLING_EDGE 	(SSP_CPHA_FALLING_EDGE<<2)
+#define	mskSSP_CPHA_RISING_EDGE		(SSP_CPHA_RISING_EDGE<<2)
+
+
+/* SSP n Clock Divider register <SSPn_CLKDIV> (0x08) */
+																		//[7:0]SSPn clock divider
+#define	SSP_DIV  								16		//MCLK/n, n = 2, 4, 6, 8, ...,512
+
+
+/* SSP n Status register <SSPn_STAT> (0x0C) */
+#define mskSSP_TX_EMPTY					(0x1<<0)		//TX FIFO empty flag
+#define mskSSP_TX_FULL					(0x1<<1)		//TX FIFO full flag
+#define mskSSP_RX_EMPTY					(0x1<<2)		//RX FIFO empty flag
+#define mskSSP_RX_FULL					(0x1<<3)		//RX FIFO full flag
+#define mskSSP_BUSY							(0x1<<4)		//Busy flag
+#define mskSSP_TXFIFOTHF				(0x1<<5)		//TX FIFO threshold flag
+#define mskSSP_RXFIFOTHF				(0x1<<6)		//RX FIFO threshold flag
+
+
+/* SSP n Interrupt Enable register <SSPn_IE> (0x10) */
+#define	SSP_RXOVFIE_DIS					0		//[0:0]RX Overflow interrupt enable
+#define	SSP_RXOVFIE_EN					1
+#define	mskSSP_RXOVFIE_DIS 			(SSP_RXOVFIE_DIS<<0)
+#define	mskSSP_RXOVFIE_EN				(SSP_RXOVFIE_EN<<0)
+
+#define	SSP_RXTOIE_DIS					0		//[1:1]RX time-out interrupt enable
+#define	SSP_RXTOIE_EN						1
+#define	mskSSP_RXTOIE_DIS 			(SSP_RXTOIE_DIS<<1)
+#define	mskSSP_RXTOIE_EN				(SSP_RXTOIE_EN<<1)
+
+#define	SSP_RXFIFOTHIE_DIS			0		//[2:2]RX FIFO threshold interrupt enable
+#define	SSP_RXFIFOTHIE_EN				1
+#define	mskSSP_RXFIFOTHIE_DIS 	(SSP_RXFIFOTHIE_DIS<<2)
+#define	mskSSP_RXFIFOTHIE_EN		(SSP_RXFIFOTHIE_EN	<<2)
+
+#define	SSP_TXFIFOTHIE_DIS			0		//[3:3]TX FIFO threshold interrupt enable
+#define	SSP_TXFIFOTHIE_EN				1
+#define	mskSSP_TXFIFOTHIE_DIS 	(SSP_TXFIFOTHIE_DIS<<3)
+#define	mskSSP_TXFIFOTHIE_EN		(SSP_TXFIFOTHIE_EN<<3)
+
+
+/* SSP n Raw Interrupt Status register <SSPn_RIS> (0x14) */
+/* SSP n Interrupt Clear register <SSPn_IC> (0x18) */
+#define mskSSP_RXOVFIF					(0x1<<0)	//[0:0]RX overflow interrupt flag
+#define mskSSP_RXOVFIC					mskSSP_RXOVFIF
+
+#define mskSSP_RXTOIF						(0x1<<1)	//[1:1]RX time-out interrupt flag
+#define mskSSP_RXTOIC						mskSSP_RXTOIF
+
+#define mskSSP_RXFIFOTHIF				(0x1<<2)	//[2:2]RX FIFO threshold interrupt flag
+#define mskSSP_RXFIFOTHIC				mskSSP_RXFIFOTHIF
+
+#define mskSSP_TXFIFOTHIF				(0x1<<3)	//[3:3]TX FIFO threshold interrupt flag
+#define mskSSP_TXFIFOTHIC				mskSSP_TXFIFOTHIF
+
+
+/*  SSP n Data Fetch register <SSPn_DF> (0x20) */
+																		//[0:0]SSP data fetch control bit
+#define	SSP_DF_DIS							0		//Disable
+#define	SSP_DF_EN								1		//Enable when SCKn frequency > 6MHz
+#define	mskSSP_DF_DIS						(SSP_DF_DIS<<0)
+#define	mskSSP_SSP_DF_EN				(SSP_DF_EN<<0)
+
+
+/*_____ M A C R O S ________________________________________________________*/
+#define	__SPI0_FIFO_RESET		(SN_SSP0->CTRL0_b.FRESET = SSP_FRESET_RESET_FIFO)
+#define	__SPI1_FIFO_RESET		(SN_SSP1->CTRL0_b.FRESET = SSP_FRESET_RESET_FIFO)
+#define	__SPI0_CLR_SEL0			(SN_GPIO1->DATA_b.DATA2=0)
+#define	__SPI0_SET_SEL0			(SN_GPIO1->DATA_b.DATA2=1)
+#define	__SPI1_CLR_SEL1			(SN_GPIO3->DATA_b.DATA6=0)
+#define	__SPI1_SET_SEL1			(SN_GPIO3->DATA_b.DATA6=1)
+//SSP Data Fetch speed (High: SCK>6MHz)
+#define	__SSP0_DATA_FETCH_HIGH_SPEED	(SN_SSP0->DF = SSP_DF_EN)		//*(volatile unsigned long *)(0x4001C020) = 1
+#define	__SSP1_DATA_FETCH_HIGH_SPEED	(SN_SSP1->DF = SSP_DF_EN)		//*(volatile unsigned long *)(0x40058020) = 1
+
+
+/*_____ D E C L A R A T I O N S ____________________________________________*/
+extern void SPI0_Init(void);
+extern void SPI0_Enable(void);
+extern void SPI0_Disable(void);
+
+extern void SPI0_Write(unsigned char *p, int len);
+#endif	/*__SN32F760_SSP_H*/
+
diff --git a/keyboards/glorious/gmmk_full/SPI0.c b/keyboards/glorious/gmmk_full/SPI0.c
@@ -0,0 +1,191 @@
+/******************** (C) COPYRIGHT 2014 SONiX *******************************
+* COMPANY:			SONiX
+* DATE:					2014/05
+* AUTHOR:				SA1
+* IC:				SN32F240/230/220
+* DESCRIPTION:	SPI0 related functions.
+*____________________________________________________________________________
+* REVISION	Date				User		Description
+* 1.0				2013/12/17	SA1			1. First release
+*	1.1				2014/05/23	SA1			1. Add __SSP0_DATA_FETCH_HIGH_SPEED macro
+*
+*____________________________________________________________________________
+* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+* WITH CODING INFORMATION REGARDING THEIR PRODUCTS TIME TO MARKET.
+* SONiX SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL
+* DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH SOFTWARE
+* AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN
+* IN CONNECTION WITH THEIR PRODUCTS.
+*****************************************************************************/
+
+/*_____ I N C L U D E S ____________________________________________________*/
+#include <SN32F260.h>
+#include "SPI.h"
+//#include "..\..\Utility\Utility.h"
+
+#define SN_SSP0 SN_SPI0
+#define SSP0_IRQn SPI0_IRQn
+
+
+/*_____ D E C L A R A T I O N S ____________________________________________*/
+
+
+/*_____ D E F I N I T I O N S ______________________________________________*/
+
+
+/*_____ M A C R O S ________________________________________________________*/
+
+
+/*_____ F U N C T I O N S __________________________________________________*/
+
+/*****************************************************************************
+* Function		: SPI0_Init
+* Description	: Initialization of SPI0 init
+* Input			: None
+* Output		: None
+* Return		: None
+* Note			: None
+*****************************************************************************/
+void SPI0_Init(void)
+{
+    /* mcu 48mhz */
+#if 1
+    SN_FLASH->LPCTRL = 0x5AFA0004;
+    SN_FLASH->LPCTRL = 0x5AFA0005;
+
+    SN_SYS0->ANBCTRL = 0x1;
+    while ((SN_SYS0->CSST & 0x1) != 0x1);
+    SN_SYS0->CLKCFG = 0x0;
+    while ((SN_SYS0->CLKCFG & 0x70) != 0x0);
+    SN_SYS0->AHBCP_b.AHBPRE = 1;
+#endif    
+
+	//Enable HCLK for SSP0
+	SN_SYS1->AHBCLKEN |= (0x1 << 12);								//Enable clock for SSP0.
+
+	//SSP0 PCLK
+	// SN_SYS1->APBCP0 |= (0x00 << 20); 								//PCLK = HCLK/1
+	//SN_SYS1->APBCP0 |= (0x01 << 20);							//PCLK = HCLK/2
+	//SN_SYS1->APBCP0 |= (0x02 << 20);							//PCLK = HCLK/4
+	//SN_SYS1->APBCP0 |= (0x03 << 20);							//PCLK = HCLK/8
+	//SN_SYS1->APBCP0 |= (0x04 << 20);							//PCLK = HCLK/16
+
+	//SSP0 setting
+	SN_SSP0->CTRL0_b.DL = SSP_DL_8;									//3 ~ 16 Data length
+	SN_SSP0->CTRL0_b.FORMAT = SSP_FORMAT_SPI_MODE;	//Interface format
+	SN_SSP0->CTRL0_b.MS = SSP_MS_MASTER_MODE;				//Master/Slave selection bit
+	SN_SSP0->CTRL0_b.LOOPBACK = SSP_LOOPBACK_DIS; 	//Loop back mode
+	SN_SSP0->CTRL0_b.SDODIS = SSP_SDODIS_EN; 				//Slave data output
+																								//(ONLY used in slave mode)
+
+	SN_SSP0->CTRL0_b.TXFIFOTH = 7;
+    // SN_SSP0->CLKDIV_b.DIV = (SSP_DIV/2) - 1;				//SSPn clock divider
+    // SN_SSP0->CLKDIV_b.DIV = 8;
+    // SN_SSP0->CLKDIV_b.DIV = 0; // 12/2 = 6MHz
+    // SN_SSP0->CLKDIV_b.DIV = 1; // 12/4 = 3MHz < SNLED2735 spec 4MHz
+    SN_SSP0->CLKDIV_b.DIV = 5;  // 48/12 = 4MHz
+
+
+	//SSP0 SPI mode
+	SN_SSP0->CTRL1 = SSP_CPHA_FALLING_EDGE|					//Clock phase for edge sampling
+									 SSP_CPOL_SCK_IDLE_LOW|					//Clock polarity selection bit
+									 SSP_MLSB_MSB;									//MSB/LSB selection bit
+
+	//SSP0 SEL0 setting
+	SN_SSP0->CTRL0_b.SELDIS = SSP_SELDIS_DIS; 			//Auto-SEL disable bit
+	//SN_GPIO1->MODE_b.MODE2=1;											//SEL(P2.15) is outout high
+	//__SPI0_SET_SEL0;
+
+	//SSP0 Fifo reset
+	__SPI0_FIFO_RESET;
+
+	//SSP0 interrupt disable
+	NVIC_DisableIRQ(SSP0_IRQn);
+
+	//__SSP0_DATA_FETCH_HIGH_SPEED;									//Enable if Freq. of SCK > 6MHz
+
+	//SSP0 enable
+	SN_SSP0->CTRL0_b.SSPEN  = SSP_SSPEN_EN;    			//SSP enable bit
+}
+
+/*****************************************************************************
+* Function		: SPI0_Enable
+* Description	: SPI0 enable setting
+* Input			: None
+* Output		: None
+* Return		: None
+* Note			: None
+*****************************************************************************/
+void SPI0_Enable(void)
+{
+	//Enable HCLK for SSP0
+	SN_SYS1->AHBCLKEN |= (0x1 << 12);								//Enable clock for SSP0.
+
+  SN_SSP0->CTRL0_b.SSPEN  = SSP_SSPEN_EN;    			//SSP enable bit
+	__SPI0_FIFO_RESET;
+
+}
+
+/*****************************************************************************
+* Function		: SPI0_Disable
+* Description	: SPI0 disable setting
+* Input			: None
+* Output		: None
+* Return		: None
+* Note			: None
+*****************************************************************************/
+void SPI0_Disable(void)
+{
+  SN_SSP0->CTRL0_b.SSPEN  = SSP_SSPEN_DIS;    		//SSP disable bit
+
+	//Disable HCLK for SSP0
+	SN_SYS1->AHBCLKEN &=~ (0x1 << 12);							//Disable clock for SSP0.
+}
+
+void SPI0_Write(unsigned char *p, int len)
+{
+    int i;
+
+    // __SPI0_CLR_SEL0;
+    //volatile uint8_t bDummyRead;
+
+    for (i = 0; i < len; i++)
+    {
+        // while(SN_SSP0->STAT_b.TX_EMPTY != 0);
+        // while(SN_SSP0->STAT_b.TX_FULL == 1);
+        while(!SN_SSP0->STAT_b.TX_EMPTY);
+        SN_SSP0->DATA_b.Data = *p++;
+        //bDummyRead = SN_SSP0->DATA_b.Data;
+        //bDummyRead++;
+        // while (SN_SSP0->STAT_b.TX_FULL == 1);
+    }
+
+    while(SN_SSP0->STAT_b.BUSY == 1);
+
+    // __SPI0_FIFO_RESET;
+
+    // __SPI0_SET_SEL0;
+}
+
+
+void SPI0_Read3(unsigned char b1, unsigned char b2, unsigned char *b3)
+{    
+    // __SPI0_CLR_SEL0;
+    //volatile uint8_t bDummyRead;
+
+        // while(SN_SSP0->STAT_b.TX_EMPTY != 0);
+        // while(SN_SSP0->STAT_b.TX_FULL == 1);
+    while(!SN_SSP0->STAT_b.TX_EMPTY);
+    SN_SSP0->DATA_b.Data = b1;
+    while(!SN_SSP0->STAT_b.TX_EMPTY);
+    SN_SSP0->DATA_b.Data = b2;
+    while(SN_SSP0->STAT_b.BUSY == 1);
+    *b3 = SN_SSP0->DATA_b.Data;
+
+    while(SN_SSP0->STAT_b.BUSY == 1);
+
+    // __SPI0_FIFO_RESET;
+
+    // __SPI0_SET_SEL0;
+}
+