SF and SW have a wrong latency

[endes0]

1 
  SF F1 0(R0)

This Assembly code should take 11 cycles to end:

• 3 for prefect+decode+reserve station
• 2 for decoding in the address ALU
• 4 in the functional unit
• 1 for write back

But It actually skips the Functional Unit.
In contrast, the following Assembly that uses loads instead of store works as intended:

1 
 LF F1 0(R0)

The same thing happens for SW and LW.