zeroize: remove unnecessary cfgs on SIMD type impls (#930)

RustCrypto · Jul 8, 2023 · 50fd775 · 50fd775
1 parent 602240f
commit 50fd775
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Showing 2 changed files with 22 additions and 36 deletions.
diff --git a/zeroize/src/aarch64.rs b/zeroize/src/aarch64.rs
@@ -8,13 +8,13 @@ use crate::{atomic_fence, volatile_write, Zeroize};
 use core::arch::aarch64::*;
 
 macro_rules! impl_zeroize_for_simd_register {
-    ($(($type:ty, $vdupq:ident)),+) => {
+    ($($type:ty),* $(,)?) => {
         $(
             #[cfg_attr(docsrs, doc(cfg(target_arch = "aarch64")))]
-            #[cfg_attr(docsrs, doc(cfg(target_feature = "neon")))]
             impl Zeroize for $type {
+                #[inline]
                 fn zeroize(&mut self) {
-                    volatile_write(self, unsafe { $vdupq(0) });
+                    volatile_write(self, unsafe { core::mem::zeroed() });
                     atomic_fence();
                 }
             }
@@ -24,12 +24,12 @@ macro_rules! impl_zeroize_for_simd_register {
 
 // TODO(tarcieri): other NEON register types?
 impl_zeroize_for_simd_register! {
-    (uint8x8_t, vdup_n_u8),
-    (uint8x16_t, vdupq_n_u8),
-    (uint16x4_t, vdup_n_u16),
-    (uint16x8_t, vdupq_n_u16),
-    (uint32x2_t, vdup_n_u32),
-    (uint32x4_t, vdupq_n_u32),
-    (uint64x1_t, vdup_n_u64),
-    (uint64x2_t, vdupq_n_u64)
+    uint8x8_t,
+    uint8x16_t,
+    uint16x4_t,
+    uint16x8_t,
+    uint32x2_t,
+    uint32x4_t,
+    uint64x1_t,
+    uint64x2_t,
 }
diff --git a/zeroize/src/x86.rs b/zeroize/src/x86.rs
@@ -9,32 +9,18 @@ use core::arch::x86::*;
 use core::arch::x86_64::*;
 
 macro_rules! impl_zeroize_for_simd_register {
-    ($type:ty, $feature:expr, $zero_value:ident) => {
-        #[cfg_attr(docsrs, doc(cfg(target_arch = "x86")))] // also `x86_64`
-        #[cfg_attr(docsrs, doc(cfg(target_feature = $feature)))]
-        impl Zeroize for $type {
-            fn zeroize(&mut self) {
-                volatile_write(self, unsafe { $zero_value() });
-                atomic_fence();
+    ($($type:ty),* $(,)?) => {
+        $(
+            #[cfg_attr(docsrs, doc(cfg(any(target_arch = "x86", target_arch = "x86_64"))))]
+            impl Zeroize for $type {
+                #[inline]
+                fn zeroize(&mut self) {
+                    volatile_write(self, unsafe { core::mem::zeroed() });
+                    atomic_fence();
+                }
             }
-        }
+        )*
     };
 }
 
-#[cfg(target_feature = "sse")]
-impl_zeroize_for_simd_register!(__m128, "sse", _mm_setzero_ps);
-
-#[cfg(target_feature = "sse2")]
-impl_zeroize_for_simd_register!(__m128d, "sse2", _mm_setzero_pd);
-
-#[cfg(target_feature = "sse2")]
-impl_zeroize_for_simd_register!(__m128i, "sse2", _mm_setzero_si128);
-
-#[cfg(target_feature = "avx")]
-impl_zeroize_for_simd_register!(__m256, "avx", _mm256_setzero_ps);
-
-#[cfg(target_feature = "avx")]
-impl_zeroize_for_simd_register!(__m256d, "avx", _mm256_setzero_pd);
-
-#[cfg(target_feature = "avx")]
-impl_zeroize_for_simd_register!(__m256i, "avx", _mm256_setzero_si256);
+impl_zeroize_for_simd_register!(__m128, __m128d, __m128i, __m256, __m256d, __m256i);