RISCY-Lib is an opensource collection of RTL (mainly SystemVerilog) design and verification Tools.
- interfaces
- A repo which contains a set of common SystemVerilog interfaces for Design and Verification
- uart_agent
- A full featured UART agent
- sram_reactive_agent
- A reactive agent acting as an SRAM block
- clk_rst_agent
- A driver agent for Clock and Reset Signals
- uart2register_layering_agent
- A UVM Layering Agent for the UART2Register Packet
- uvm_utils
- A collection of useful UVM headers
- colored_reporter
- A UVM Report Server which adds color to outputs
- uart2sram
- A module which converts the UART2Register Packet to an SRAM interface
