RP2350: Add RISCV, Unify RP2350, Update UART, Add XH3IRQ Interrupt Controller #21753

AnnsAnns · 2025-09-30T14:24:50Z

Contribution description

After two failed attempts, I finally managed to get a shared and unified setup working for the RP2350. As opposed to the other approaches I took, where I tried to fully unify both the RISCV and ARM versions, this version takes a different approach similar to cortexm_common or riscv_common where each CPU still exists as a separate entity, e.g. rp2350_arm and rp2350_riscv but uses the shared rp2350_common folder.

This PR supersedes both #21745 and #21746, as in it:

adds support for the Hazard3 CPU used on the RP2350
adds support for the XH3IRQ Interrupt Controller used by the Hazard3. While fairly similar to CLIC/PLIC, the Hazard3 on the RP2350 actually has a custom interrupt controller to "mimick" the way interrupts work on the Cortex ARM side, even having support for direct vector table jumps (Not enabled here since I wanted to still use the trap_entry/trap_handler of riscv_common.
updates the uart
enables interrupts on the CortexM33
unifies both the RISCV and ARM side of the RP2350
renames rp2350 (arm version) to rp2350_arm
renames rpi-pico-2 (arm version) to rpi-pico-2-arm
fixes debugging completely (GDB now runs smoothly both on ARM and RISCV)

However, as of now, it does not yet add the multicore example. All the points raised in the other PRs also still hold true.

Testing procedure

Remember to specify USEMODULE += stdio_uart if you wish to print via UART.

For my testing I mostly modified examples/basic/blinky to also print. On RISCV you can also use xh3irq_force_irq to force interrupts for testing purposes, for example, on each blinky loop, if you feel like it :)

RISCV

make PROGRAMMER=openocd QUIET=0 BOARD=rpi-pico-2-riscv flash flashes the pico 2 in RISCV mode using openocd, you can also use make PROGRAMMER=picotool QUIET=0 BOARD=rpi-pico-2-riscv flash to flash it using picotool.

ARM

make PROGRAMMER=openocd QUIET=0 BOARD=rpi-pico-2-arm flash flashes the pico 2 in RISCV mode using openocd, you can also use make PROGRAMMER=picotool QUIET=0 BOARD=rpi-pico-2-arm flash to flash it using picotool.

Issues/PRs references

crasbe · 2025-09-30T14:27:29Z

Would you mind creating a "DELETEME" commit that adds the two boards to the .murdock file, so that the CI tests actually are meaningful? :)

boards/rpi-pico-2-arm/include/periph_conf.h

cpu/riscv_common/irq_arch.c

cpu/rp2350_riscv/Makefile.features

cpu/rp2350_riscv/picobin_block.s

features.yaml

boards/rpi-pico-2-riscv/doc.md

riot-ci · 2025-09-30T16:07:38Z

Murdock results

❌ FAILED

cca4d4f DELETEME

Build failures (21)

Application	Target	Toolchain	Runtime (s)	Worker
examples/basic/default	rpi-pico-2-riscv	gnu	1.83	mobi7
tests/bench/sizeof_coretypes	rpi-pico-2-riscv	gnu	1.65	mobi7
tests/core/msg_avail	rpi-pico-2-riscv	gnu	2.26	mobi6
tests/core/mutex_order	rpi-pico-2-riscv	gnu	2.25	mobi6
tests/core/sched_change_priority	rpi-pico-2-riscv	gnu	1.79	mobi7
tests/core/thread_flags_group	rpi-pico-2-riscv	gnu	1.79	tatooine
tests/core/thread_msg_block_w_queue	rpi-pico-2-riscv	gnu	2.07	mobi6
tests/core/thread_msg_bus	rpi-pico-2-riscv	gnu	2.22	mobi6
tests/drivers/disp_dev	rpi-pico-2-riscv	gnu	1.90	mobi7
tests/pkg/jsmn	rpi-pico-2-riscv	gnu	1.76	tatooine
tests/pkg/mcufont	rpi-pico-2-riscv	gnu	1.57	tatooine
tests/sys/cb_mux	rpi-pico-2-arm	gnu	2.48	skyleaf
tests/sys/event_source	rpi-pico-2-riscv	gnu	2.29	tud-1
tests/sys/malloc	rpi-pico-2-riscv	gnu	1.92	skyleaf
tests/sys/od	rpi-pico-2-riscv	gnu	2.25	mobi6
tests/sys/shell_coreclk	rpi-pico-2-riscv	gnu	1.93	skyleaf
tests/sys/ssp	rpi-pico-2-riscv	gnu	1.63	mobi7
tests/sys/struct_tm_utility	rpi-pico-2-riscv	gnu	2.09	mobi6
tests/sys/vfs_iterate_mount	rpi-pico-2-riscv	gnu	1.91	skyleaf
tests/turo	rpi-pico-2-riscv	gnu	1.70	mobi7

and 297 more build failures...

Artifacts

boards/rpi-pico-2-arm/include/board.h

mguetschow

Great work! 🎉 Some comments from briefly skimming over the changes.

boards/rpi-pico-2-arm/include/periph_conf.h

boards/rpi-pico-2-riscv/board.c

boards/rpi-pico-2-riscv/dist/openocd.cfg

boards/rpi-pico-2-riscv/doc.md

mguetschow · 2025-09-30T17:41:05Z

boards/rpi-pico-2-riscv/include/periph_conf.h

Isn't that the exact same file as in boards/rpi-pico-2-riscv?

Yes, I just wasn't too sure how to handle the boards, technically I could also do the rpi-pico-2-common strategy but also like, there is barely any code here (Though I guess doing that would futureproof it)

Is a rpi-pico-2-common folder something that makes sense in this context currently?

For boards, the common parts are in the subfolder boards/common, so in this case boards/common/rpi-pico-2.

Created a common boards folder 👍

cpu/rp2350_common/include/periph_cpu.h

cpu/rp2350_common/periph/uart.c

mguetschow · 2025-09-30T17:58:19Z

cpu/rp2350_common/periph/uart.c

+    // case UART_PARITY_EVEN:
+    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk);
+    //     break;
+    // case UART_PARITY_ODD:
+    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk);
+    //     break;


I'd actually argue those are fine, if they are not actual comments, but more or less temporarily commenting out part of the code. The question is rather why it is commented out, an additional comment would help :)

cpu/rp2350_common/periph/uart.c

AnnsAnns

Thank you for all the reviews (esp. so quickly 🐎), I will try to go through all the points mentioned and fix them 🐸 👉👉

boards/rpi-pico-2-arm/include/periph_conf.h

boards/rpi-pico-2-riscv/board.c

boards/rpi-pico-2-riscv/dist/openocd.cfg

boards/rpi-pico-2-riscv/doc.md

AnnsAnns · 2025-10-01T09:27:27Z

cpu/rp2350_common/periph/uart.c

+    // case UART_PARITY_EVEN:
+    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk);
+    //     break;
+    // case UART_PARITY_ODD:
+    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk);
+    //     break;


Uh quite frankly because I never tested these configurations and there were still issues with different define names between cpu/rp2040 and RP2350.h

cpu/rp2350_common/periph/uart.c

boards/rpi-pico-2-arm/dist/openocd.cfg

boards/rpi-pico-2-arm/include/board.h

crasbe · 2025-10-01T13:26:08Z

cpu/riscv_common/irq_arch.c

+
+    if ((mcause & ~MCAUSE_INT) <= 0xb) {
+        const char *error_messages[] = {
+            "Instruction alignment: Does not occur on RP2350, because 16-bit compressed instructions are implemented, and it is impossible to jump to a byte-aligned address.",


Suggested change

"Instruction alignment: Does not occur on RP2350, because 16-bit compressed instructions are implemented, and it is impossible to jump to a byte-aligned address.",

"Instruction alignment: Does not occur on RP2350, because "

"16-bit compressed instructions are implemented, and it is "

"impossible to jump to a byte-aligned address.",

Perhaps you can split the other lines up too? C allows you to do that:
https://stackoverflow.com/a/797351

Updated the entire function to be a bit less hacky (The error messages were straight out of the rp2350 documentation, the new one follows the official RISC-V specs https://riscv.github.io/riscv-isa-manual/snapshot/privileged/#mcause)

If you want to be fancy, you can also add a comment with that link to the code 🤔

Fancy fancy

cpu/riscv_common/irq_arch.c

AnnsAnns · 2025-10-01T14:53:30Z

Moving the register addresses out of the assembly caused the assembler to complain. Since that is the only location they are used I moved them back into the function and simply explained them within the function.

boards/rpi-pico-2-riscv/include/periph_conf.h

cpu/riscv_common/include/xh3irq.h

cpu/riscv_common/irq_arch.c

cpu/rp2350_riscv/include/cpu_conf.h

cpu/rp2350_riscv/include/core_cm33.h

cpu/riscv_common/include/xh3irq.h

cpu/rp2350_arm/cpu.c

cpu/rp2350_common/periph/uart.c

crasbe · 2025-10-02T10:01:06Z

I resolved some of the review comments that were fixed, but here are the ones that either haven't been addressed yet or where I'm not sure if they should be marked as resolved yet.

#21753 (comment)
#21753 (comment)
#21753 (comment)
#21753 (comment)
#21753 (comment)
#21753 (comment)

cpu/riscv_common/irq_arch.c

cpu/riscv_common/include/xh3irq.h

cpu/riscv_common/irq_arch.c

cpu/riscv_common/periph/xh3irq.c

cpu/rp2350_arm/include/cpu_conf.h

cpu/rp2350_common/include/compat_layer.h

cpu/rp2350_riscv/include/cpu_conf.h

AnnsAnns · 2025-10-06T10:50:13Z

It appears like the culprit was similar to the issue I had before, the riscv interrupt entry expects the scheduler to be active before going into interrupts, since we initialized the rp2350 uart, etc. before that it could cause the uart to trigger and already queue before exiting the cpu_init function. Simply enabling interrupts as the last part of the cpu_init appears to mitigate that issue.

cpu/rp2350_common/periph/uart.c

AnnsAnns · 2025-10-06T11:07:06Z

I resolved some of the review comments that were fixed, but here are the ones that either haven't been addressed yet or where I'm not sure if they should be marked as resolved yet.

#21753 (comment) #21753 (comment) #21753 (comment) #21753 (comment) #21753 (comment) #21753 (comment)

Tracking:

cpu/rp2350_common/include/compat_layer.h

AnnsAnns · 2025-10-06T14:15:21Z

Its hard to keep track with Github but I think I should have covered all feedback, thank you for all the reviews so far 🙏

boards/rpi-pico-2-arm/Makefile

boards/Makefile

crasbe

I think though you can do an intermediate squash already. Or you can squash everything at the very end, however you prefer.

Hopefully I'll get around testing it on real hardware soon.

crasbe · 2025-10-07T14:59:06Z

cpu/rp2350_arm/Makefile.include

+CFLAGS += -D$(CPU_MODEL)
+CFLAGS += -DROM_START_ADDR=$(ROM_START_ADDR)
+CFLAGS += -DRAM_START_ADDR=$(RAM_START_ADDR)
+CFLAGS += -Wno-error


Suggested change

CFLAGS += -Wno-error

crasbe · 2025-10-07T14:59:45Z

cpu/rp2350_common/Makefile.include

@@ -1,33 +1,17 @@
+CFLAGS += -Wno-pedantic


Suggested change

CFLAGS += -Wno-pedantic

I guess?

crasbe · 2025-10-07T15:00:34Z

cpu/rp2350_common/cpu.c

 *
- * @file
- * @brief           CPU initialization implementation for the RP2350
+ * @file        cpu.c


Suggested change

* @file cpu.c

* @file

I think this is not necessary.

AnnsAnns · 2025-10-07T21:20:36Z

Will do a squash tomorrow, I also updated the UART to be fairly feature complete now after a full day of debugging a really weird UART reading issue only to find out that the pins were swapped on my adapter (but for some reason UART writing still worked, its really cursed and I dont want to question it anymore [Thank you to Teufelchen for surviving this insanity with me])

AnnsAnns · 2025-10-08T11:28:27Z

That rebase went like, wrong wrong wow, the amount of fixups overwhelmed it. I will fix it and re-push it.

AnnsAnns · 2025-10-08T12:02:56Z

Not really sure what triggers this but rebase kept creating multiple identical commits in the process of rebasing.

After lunch I'll diff the pushed commits just to ensure that I didn't accidentally regress anything in the process.

AnnsAnns requested review from leandrolanzieri, jia200x and MrKevinWeiss as code owners September 30, 2025 14:24

github-actions bot added Area: doc Area: Documentation Area: build system Area: Build system Area: boards Area: Board ports Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms Area: cpu Area: CPU/MCU ports Area: Kconfig Area: Kconfig integration labels Sep 30, 2025

AnnsAnns mentioned this pull request Sep 30, 2025

RP2350 (RISCV): Add initial support & XH3IRQ Interrupt Controller support #21745

Closed

crasbe added Type: new feature The issue requests / The PR implemements a new feature for RIOT CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR labels Sep 30, 2025

AnnsAnns mentioned this pull request Sep 30, 2025

RP2350 (ARM): Multicore Support, Interrupts, UART updates and better debugging #21746

Closed

AnnsAnns requested a review from kaspar030 as a code owner September 30, 2025 14:30

github-actions bot added the Area: CI Area: Continuous Integration of RIOT components label Sep 30, 2025

crasbe reviewed Sep 30, 2025

View reviewed changes

boards/rpi-pico-2-riscv/doc.md Show resolved Hide resolved

mguetschow reviewed Sep 30, 2025

View reviewed changes

boards/rpi-pico-2-arm/include/board.h Outdated Show resolved Hide resolved

mguetschow requested changes Sep 30, 2025

View reviewed changes

AnnsAnns commented Oct 1, 2025

View reviewed changes

crasbe added the CI: no fast fail don't abort PR build after first error label Oct 1, 2025

crasbe reviewed Oct 1, 2025

View reviewed changes

boards/rpi-pico-2-arm/dist/openocd.cfg Outdated Show resolved Hide resolved

crasbe reviewed Oct 1, 2025

View reviewed changes

cpu/riscv_common/irq_arch.c Outdated Show resolved Hide resolved

crasbe reviewed Oct 1, 2025

View reviewed changes

crasbe reviewed Oct 2, 2025

View reviewed changes

crasbe reviewed Oct 6, 2025

View reviewed changes

cpu/rp2350_common/periph/uart.c Outdated Show resolved Hide resolved

crasbe reviewed Oct 6, 2025

View reviewed changes

cpu/rp2350_common/include/compat_layer.h Show resolved Hide resolved

crasbe reviewed Oct 6, 2025

View reviewed changes

boards/rpi-pico-2-arm/Makefile Outdated Show resolved Hide resolved

crasbe reviewed Oct 6, 2025

View reviewed changes

boards/Makefile Show resolved Hide resolved

crasbe reviewed Oct 7, 2025

View reviewed changes

AnnsAnns force-pushed the rp2350_common_the_third_and_final branch from ceef12d to 8a0ad0e Compare October 8, 2025 11:23

boards/rpi-pico-2-riscv: add riscv based rp2350 board

1c64ce1

AnnsAnns force-pushed the rp2350_common_the_third_and_final branch from 8a0ad0e to 2058fce Compare October 8, 2025 11:46

AnnsAnns added 15 commits October 8, 2025 13:59

cpu/rp2350_riscv: add initial support

72d9dc1

cpu/riscv_common: Add periph xh3irq support

7e01826

cpu/rp2350_riscv: add xh3irq support

60d67b2

cpu/rp2350: move to new uart

f5329d0

cpu/rp2350_common: create shared folder for RISCV & ARM

41f1088

cpu/rp2350_riscv: move to shared rp2350_common

f93e7eb

boards/rpi-pico-2: adjust to new rp2350_arm name

06d4bf2

boards/rpi-pico-2: rename arm pico 2 version to rpi-pico-2-arm

d73c905

cpu/rp2350_common: change register calculation functions to pointers

14020a6

boards/rpi-pico-2: unify doc.md into one singular doc.md

862699e

pkg/picosdk: Add patch for bit overlap

849e732

boards/rpi-pico-2-*: create common board folder

8733ca1

cpu/rp2350: increase stack size

f831b8d

cpu/rp2350: provide pmp

f6fb015

DELETEME

cca4d4f

AnnsAnns force-pushed the rp2350_common_the_third_and_final branch from 2058fce to cca4d4f Compare October 8, 2025 12:00

-            "Instruction alignment: Does not occur on RP2350, because 16-bit compressed instructions are implemented, and it is impossible to jump to a byte-aligned address.",
+            "Instruction alignment: Does not occur on RP2350, because "
+            "16-bit compressed instructions are implemented, and it is "
+            "impossible to jump to a byte-aligned address.",

RP2350: Add RISCV, Unify RP2350, Update UART, Add XH3IRQ Interrupt Controller #21753

Are you sure you want to change the base?

RP2350: Add RISCV, Unify RP2350, Update UART, Add XH3IRQ Interrupt Controller #21753

Conversation

AnnsAnns commented Sep 30, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Contribution description

Testing procedure

RISCV

ARM

Issues/PRs references

Uh oh!

crasbe commented Sep 30, 2025

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

riot-ci commented Sep 30, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Murdock results

Artifacts

Uh oh!

Uh oh!

mguetschow left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

AnnsAnns left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

AnnsAnns commented Sep 30, 2025 •

edited

Loading

riot-ci commented Sep 30, 2025 •

edited

Loading

AnnsAnns commented Oct 6, 2025 •

edited

Loading

AnnsAnns commented Oct 7, 2025 •

edited

Loading

AnnsAnns commented Oct 8, 2025 •

edited

Loading