convert to verilog with ghdl

COMPARATOR_16BIT.v

@@ -0,0 +1,32 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module COMPARATOR_16BIT(clk, din, sel, comp_val, pwm_o);
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  wire _3_;
+  wire _4_;
+  wire _5_;
+  wire _6_;
+  reg _7_;
+  input clk;
+  wire clk;
+  input [15:0] comp_val;
+  wire [15:0] comp_val;
+  input [15:0] din;
+  wire [15:0] din;
+  output pwm_o;
+  wire pwm_o;
+  input sel;
+  wire sel;
+  assign _4_ = _3_ ? 1'h1 : 1'h0;
+  assign _5_ = sel ? _4_ : _7_;
+  assign _6_ = _0_ ? _2_ : _5_;
+  always @(posedge clk)
+    _7_ <= _6_;
+  assign _0_ = ~ sel;
+  assign _1_ = din >= comp_val;
+  assign _2_ = _1_ ? 1'h0 : 1'h1;
+  assign _3_ = din <= comp_val;
+  assign pwm_o = _7_;
+endmodule

COUNTER_16BIT.v

@@ -0,0 +1,44 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module COUNTER_16BIT(clk, en, rst, overflow, dout, ndout);
+  wire [31:0] _0_;
+  reg _1_;
+  wire _2_;
+  wire _3_;
+  wire [15:0] _4_;
+  wire [15:0] _5_;
+  reg [15:0] _6_ = 16'h0000;
+  wire _7_;
+  wire _8_;
+  wire _9_;
+  input clk;
+  wire clk;
+  wire [15:0] cnt_reg;
+  output [15:0] dout;
+  wire [15:0] dout;
+  input en;
+  wire en;
+  output [15:0] ndout;
+  wire [15:0] ndout;
+  output overflow;
+  wire overflow;
+  input rst;
+  wire rst;
+  assign _2_ = { 16'h0000, cnt_reg } == 32'd0;
+  assign _3_ = _2_ ? 1'h1 : 1'h0;
+  assign _4_ = ~ cnt_reg;
+  assign _5_ = en ? _0_[15:0] : cnt_reg;
+  always @(posedge clk, posedge rst)
+    if (rst) _6_ <= 16'h0000;
+    else _6_ <= _5_;
+  assign _7_ = ~ rst;
+  assign _8_ = en & _7_;
+  assign _9_ = _8_ ? _3_ : _1_;
+  always @(posedge clk)
+    _1_ <= _9_;
+  assign _0_ = { 16'h0000, cnt_reg } + 32'd1;
+  assign cnt_reg = _6_;
+  assign overflow = _1_;
+  assign dout = cnt_reg;
+  assign ndout = _4_;
+endmodule

FREQCOUNT_CORE_V4.v

@@ -0,0 +1,122 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module FREQCOUNT_CORE_V4(clk, rst, en, cnt_clk, int_ack, interval_time, \int , freq);
+  wire _00_;
+  wire _01_;
+  wire [31:0] _02_;
+  wire _03_;
+  wire _04_;
+  wire _05_;
+  wire [3:0] _06_;
+  reg [3:0] _07_;
+  wire _08_;
+  reg _09_;
+  wire _10_;
+  wire _11_;
+  wire _12_;
+  wire _13_;
+  reg _14_;
+  wire [26:0] _15_;
+  reg [26:0] _16_ = 27'h0000000;
+  wire _17_;
+  reg _18_;
+  wire [31:0] _19_;
+  reg [31:0] _20_;
+  wire _21_;
+  wire [31:0] _22_;
+  wire _23_;
+  wire [31:0] _24_;
+  reg [31:0] _25_;
+  wire [26:0] _26_;
+  wire _27_;
+  wire _28_;
+  wire [26:0] _29_;
+  wire _30_;
+  wire _31_;
+  input clk;
+  wire clk;
+  input cnt_clk;
+  wire cnt_clk;
+  wire cnt_en;
+  wire [31:0] cnt_reg;
+  wire cnt_rst;
+  input en;
+  wire en;
+  wire [3:0] flipflop_delay;
+  output [31:0] freq;
+  wire [31:0] freq;
+  output \int ;
+  wire \int ;
+  input int_ack;
+  wire int_ack;
+  wire interrupt;
+  wire [26:0] interval;
+  input [31:0] interval_time;
+  wire [31:0] interval_time;
+  input rst;
+  wire rst;
+  assign _22_ = { 5'h00, interval } + 32'd1;
+  assign _26_ = _11_ ? interval : _22_[26:0];
+  assign _27_ = _11_ ? 1'h1 : interrupt;
+  assign _28_ = int_ack ? 1'h1 : 1'h0;
+  assign _29_ = int_ack ? 27'h0000000 : _26_;
+  assign _30_ = int_ack ? 1'h0 : _27_;
+  assign _31_ = cnt_rst | rst;
+  assign _01_ = en & cnt_en;
+  assign _02_ = cnt_reg + 32'd1;
+  assign _00_ = en & _11_;
+  assign _03_ = flipflop_delay[3:1] == 3'h0;
+  assign _04_ = flipflop_delay[3:1] == 3'h7;
+  function [0:0] \58 ;
+    input [0:0] a;
+    input [1:0] b;
+    input [1:0] s;
+    (* parallel_case *)
+    casez (s)
+      2'b?1:
+        \58  = b[0:0];
+      2'b1?:
+        \58  = b[1:1];
+      default:
+        \58  = a;
+    endcase
+  endfunction
+  assign _05_ = \58 (cnt_en, 2'h1, { _04_, _03_ });
+  assign _06_ = en ? { flipflop_delay[2:0], interrupt } : flipflop_delay;
+  always @(posedge cnt_clk)
+    _07_ <= _06_;
+  assign _08_ = en ? _05_ : cnt_en;
+  always @(posedge cnt_clk)
+    _09_ <= _08_;
+  assign _10_ = ~ rst;
+  assign _12_ = en & _10_;
+  assign _13_ = _12_ ? _28_ : cnt_rst;
+  always @(posedge clk)
+    _14_ <= _13_;
+  assign _11_ = { 5'h00, interval } == interval_time;
+  assign _15_ = en ? _29_ : interval;
+  always @(posedge clk, posedge rst)
+    if (rst) _16_ <= 27'h0000000;
+    else _16_ <= _15_;
+  assign _17_ = en ? _30_ : interrupt;
+  always @(posedge clk, posedge rst)
+    if (rst) _18_ <= 1'h0;
+    else _18_ <= _17_;
+  assign _19_ = _01_ ? _02_ : cnt_reg;
+  always @(posedge cnt_clk, posedge _31_)
+    if (_31_) _20_ <= 32'd0;
+    else _20_ <= _19_;
+  assign _21_ = ~ rst;
+  assign _23_ = _00_ & _21_;
+  assign _24_ = _23_ ? cnt_reg : _25_;
+  always @(posedge clk)
+    _25_ <= _24_;
+  assign flipflop_delay = _07_;
+  assign cnt_en = _09_;
+  assign cnt_rst = _14_;
+  assign interval = _16_;
+  assign interrupt = _18_;
+  assign cnt_reg = _20_;
+  assign \int  = interrupt;
+  assign freq = _25_;
+endmodule

PWM_CORE_LAT_V17.v

@@ -0,0 +1,73 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module PWM_CORE_LAT_V17(clk, rst, en, pwm_reg_a, pwm_reg_b, pwm_out_1, pwm_out_2);
+  wire [15:0] _0_;
+  wire [15:0] _1_;
+  wire _2_;
+  wire [15:0] _3_;
+  wire [15:0] _4_;
+  wire _5_;
+  wire _6_;
+  input clk;
+  wire clk;
+  wire counter_overflow;
+  input en;
+  wire en;
+  wire [15:0] n_counter_val;
+  wire [15:0] p_counter_val;
+  output pwm_out_1;
+  wire pwm_out_1;
+  output pwm_out_2;
+  wire pwm_out_2;
+  input [15:0] pwm_reg_a;
+  wire [15:0] pwm_reg_a;
+  input [15:0] pwm_reg_b;
+  wire [15:0] pwm_reg_b;
+  wire [15:0] reg_a_out;
+  wire [15:0] reg_b_out;
+  input rst;
+  wire rst;
+  COUNTER_16BIT counter (
+    .clk(clk),
+    .dout(_3_),
+    .en(en),
+    .ndout(_4_),
+    .overflow(_2_),
+    .rst(rst)
+  );
+  COMPARATOR_16BIT n_comparator (
+    .clk(clk),
+    .comp_val(reg_b_out),
+    .din(n_counter_val),
+    .pwm_o(_6_),
+    .sel(1'h1)
+  );
+  COMPARATOR_16BIT p_comparator (
+    .clk(clk),
+    .comp_val(reg_a_out),
+    .din(p_counter_val),
+    .pwm_o(_5_),
+    .sel(1'h0)
+  );
+  REGISTER_16BIT reg_a (
+    .clk(clk),
+    .din(pwm_reg_a),
+    .dout(_0_),
+    .en(counter_overflow),
+    .rst(rst)
+  );
+  REGISTER_16BIT reg_b (
+    .clk(clk),
+    .din(pwm_reg_b),
+    .dout(_1_),
+    .en(counter_overflow),
+    .rst(rst)
+  );
+  assign n_counter_val = _4_;
+  assign p_counter_val = _3_;
+  assign reg_a_out = _0_;
+  assign reg_b_out = _1_;
+  assign counter_overflow = _2_;
+  assign pwm_out_1 = _5_;
+  assign pwm_out_2 = _6_;
+endmodule

REGISTER_16BIT.v

@@ -0,0 +1,23 @@
+/* Generated by Yosys 0.29+11 (git sha1 acfdc5cc4, clang 10.0.0-4ubuntu1 -fPIC -Os) */
+
+module REGISTER_16BIT(clk, rst, en, din, dout);
+  wire [15:0] _0_;
+  reg [15:0] _1_;
+  input clk;
+  wire clk;
+  input [15:0] din;
+  wire [15:0] din;
+  output [15:0] dout;
+  wire [15:0] dout;
+  input en;
+  wire en;
+  wire [15:0] \reg ;
+  input rst;
+  wire rst;
+  always @(posedge clk, posedge rst)
+    if (rst) _1_ <= 16'h0000;
+    else _1_ <= _0_;
+  assign _0_ = en ? din : \reg ;
+  assign \reg  = _1_;
+  assign dout = \reg ;
+endmodule