OpenSource16bitRISC

16 bit RISC machine

Machine was built in may 2016.

Email me if you are serious developer and want to improve this machine.

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
.lso		.lso
ALU.prj		ALU.prj
ALU.stx		ALU.stx
ALU.xst		ALU.xst
ALU_MUX_UNIT.vhd		ALU_MUX_UNIT.vhd
ALU_RESULT_STORAGE.vhd		ALU_RESULT_STORAGE.vhd
ALU_RESULT_STORAGE_vhdl.prj		ALU_RESULT_STORAGE_vhdl.prj
ALU_TEST.vhd		ALU_TEST.vhd
ALU_summary.html		ALU_summary.html
ALU_vhdl.prj		ALU_vhdl.prj
ArithmeticOperations_Unit.prj		ArithmeticOperations_Unit.prj
ArithmeticOperations_Unit.stx		ArithmeticOperations_Unit.stx
ArithmeticOperations_Unit.xst		ArithmeticOperations_Unit.xst
ArithmeticOperations_Unit_vhdl.prj		ArithmeticOperations_Unit_vhdl.prj
BRANCH_CONTROLLER.prj		BRANCH_CONTROLLER.prj
BRANCH_CONTROLLER.stx		BRANCH_CONTROLLER.stx
BRANCH_CONTROLLER.vhd		BRANCH_CONTROLLER.vhd
BRANCH_CONTROLLER.xst		BRANCH_CONTROLLER.xst
BRANCH_CONTROLLER_vhdl.prj		BRANCH_CONTROLLER_vhdl.prj
Branc_Unit.vhd		Branc_Unit.vhd
Branch_Unit.prj		Branch_Unit.prj
Branch_Unit.stx		Branch_Unit.stx
Branch_Unit.vhd		Branch_Unit.vhd
Branch_Unit.xst		Branch_Unit.xst
Branch_Unit_vhdl.prj		Branch_Unit_vhdl.prj
CALCULATE_EXTERNAL_MEM_ADDR_UNIT.prj		CALCULATE_EXTERNAL_MEM_ADDR_UNIT.prj
CALCULATE_EXTERNAL_MEM_ADDR_UNIT.stx		CALCULATE_EXTERNAL_MEM_ADDR_UNIT.stx
CALCULATE_EXTERNAL_MEM_ADDR_UNIT.vhd		CALCULATE_EXTERNAL_MEM_ADDR_UNIT.vhd
CALCULATE_EXTERNAL_MEM_ADDR_UNIT.xst		CALCULATE_EXTERNAL_MEM_ADDR_UNIT.xst
CALCULATE_EXTERNAL_MEM_ADDR_UNIT_vhdl.prj		CALCULATE_EXTERNAL_MEM_ADDR_UNIT_vhdl.prj
CLOCK_CONTROLLER_TEST_beh.prj		CLOCK_CONTROLLER_TEST_beh.prj
CLOCK_CONTROLLER_TEST_isim_beh.exe		CLOCK_CONTROLLER_TEST_isim_beh.exe
CLOCK_CONTROLLER_TEST_isim_beh.wdb		CLOCK_CONTROLLER_TEST_isim_beh.wdb
CLOCK_CONTROLLER_TEST_isim_beh1.wdb		CLOCK_CONTROLLER_TEST_isim_beh1.wdb
Clock_Controller.prj		Clock_Controller.prj
Clock_Controller.stx		Clock_Controller.stx
Clock_Controller.vhd		Clock_Controller.vhd
Clock_Controller.xst		Clock_Controller.xst
Clock_Controller_isim_beh1.wdb		Clock_Controller_isim_beh1.wdb
Clock_Controller_vhdl.prj		Clock_Controller_vhdl.prj
Control_Unit_vhdl.prj		Control_Unit_vhdl.prj
DATA_Controller.prj		DATA_Controller.prj
DATA_Controller.stx		DATA_Controller.stx
DATA_Controller.vhd		DATA_Controller.vhd
DATA_Controller.xst		DATA_Controller.xst
DATA_Controller_vhdl.prj		DATA_Controller_vhdl.prj
DATA_HAZARD_CONTROLLER.prj		DATA_HAZARD_CONTROLLER.prj
DATA_HAZARD_CONTROLLER.stx		DATA_HAZARD_CONTROLLER.stx
DATA_HAZARD_CONTROLLER.vhd		DATA_HAZARD_CONTROLLER.vhd
DATA_HAZARD_CONTROLLER.xst		DATA_HAZARD_CONTROLLER.xst
DATA_HAZARD_CONTROLLER_vhdl.prj		DATA_HAZARD_CONTROLLER_vhdl.prj
DATA_MEMORY.prj		DATA_MEMORY.prj
DATA_MEMORY.stx		DATA_MEMORY.stx
DATA_MEMORY.vhd		DATA_MEMORY.vhd
DATA_MEMORY.xst		DATA_MEMORY.xst
DATA_MEMORY_ADDR_MUX.prj		DATA_MEMORY_ADDR_MUX.prj
DATA_MEMORY_ADDR_MUX.stx		DATA_MEMORY_ADDR_MUX.stx
DATA_MEMORY_ADDR_MUX.vhd		DATA_MEMORY_ADDR_MUX.vhd
DATA_MEMORY_ADDR_MUX.xst		DATA_MEMORY_ADDR_MUX.xst
DATA_MEMORY_ADDR_MUX_vhdl.prj		DATA_MEMORY_ADDR_MUX_vhdl.prj
DATA_MEMORY_ADDR_STORAGE.prj		DATA_MEMORY_ADDR_STORAGE.prj
DATA_MEMORY_ADDR_STORAGE.stx		DATA_MEMORY_ADDR_STORAGE.stx
DATA_MEMORY_ADDR_STORAGE.vhd		DATA_MEMORY_ADDR_STORAGE.vhd
DATA_MEMORY_ADDR_STORAGE.xst		DATA_MEMORY_ADDR_STORAGE.xst
DATA_MEMORY_ADDR_STORAGE_vhdl.prj		DATA_MEMORY_ADDR_STORAGE_vhdl.prj
DATA_MEMORY_WRITE_ADDR_FIXER.prj		DATA_MEMORY_WRITE_ADDR_FIXER.prj
DATA_MEMORY_WRITE_ADDR_FIXER.stx		DATA_MEMORY_WRITE_ADDR_FIXER.stx
DATA_MEMORY_WRITE_ADDR_FIXER.vhd		DATA_MEMORY_WRITE_ADDR_FIXER.vhd
DATA_MEMORY_WRITE_ADDR_FIXER.xst		DATA_MEMORY_WRITE_ADDR_FIXER.xst
DATA_MEMORY_WRITE_ADDR_FIXER_vhdl.prj		DATA_MEMORY_WRITE_ADDR_FIXER_vhdl.prj
DATA_MEMORY_beh.prj		DATA_MEMORY_beh.prj
DATA_MEMORY_isim_beh.exe		DATA_MEMORY_isim_beh.exe
DATA_MEMORY_isim_beh.wdb		DATA_MEMORY_isim_beh.wdb
DATA_MEMORY_vhdl.prj		DATA_MEMORY_vhdl.prj
DEC_REGISTER.cmd_log		DEC_REGISTER.cmd_log
DEC_REGISTER.vhd		DEC_REGISTER.vhd
DEC_REGISTER_vhdl.prj		DEC_REGISTER_vhdl.prj
DEC_STR.vhd		DEC_STR.vhd
DELAYED_CHECK_FLAG.prj		DELAYED_CHECK_FLAG.prj
DELAYED_CHECK_FLAG.stx		DELAYED_CHECK_FLAG.stx
DELAYED_CHECK_FLAG.vhd		DELAYED_CHECK_FLAG.vhd
DELAYED_CHECK_FLAG.xst		DELAYED_CHECK_FLAG.xst
DELAYED_CHECK_FLAG_vhdl.prj		DELAYED_CHECK_FLAG_vhdl.prj
DELAYING_JUMP_ADDR_FOR_RB_MUX_BRANCH.prj		DELAYING_JUMP_ADDR_FOR_RB_MUX_BRANCH.prj
DELAYING_JUMP_ADDR_FOR_RB_MUX_BRANCH.stx		DELAYING_JUMP_ADDR_FOR_RB_MUX_BRANCH.stx
DELAYING_JUMP_ADDR_FOR_RB_MUX_BRANCH.vhd		DELAYING_JUMP_ADDR_FOR_RB_MUX_BRANCH.vhd
DELAYING_JUMP_ADDR_FOR_RB_MUX_BRANCH.xst		DELAYING_JUMP_ADDR_FOR_RB_MUX_BRANCH.xst
DELAYING_JUMP_ADDR_FOR_RB_MUX_BRANCH_vhdl.prj		DELAYING_JUMP_ADDR_FOR_RB_MUX_BRANCH_vhdl.prj
D_reg_vhdl.prj		D_reg_vhdl.prj
Decoder_Test.vhd		Decoder_Test.vhd
Decoding_Unit.prj		Decoding_Unit.prj
Decoding_Unit.stx		Decoding_Unit.stx
Decoding_Unit.vhd		Decoding_Unit.vhd
Decoding_Unit.xst		Decoding_Unit.xst
Decoding_Unit_summary.html		Decoding_Unit_summary.html
Decoding_Unit_vhdl.prj		Decoding_Unit_vhdl.prj
LICENSE		LICENSE
README.md		README.md
Reg_Bank.vhd		Reg_Bank.vhd
clock_controller_test.vhd		clock_controller_test.vhd

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