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feat(FTB, FTQ): split FTB meta SRAM and FTQ meta SRAM #4360

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feat(FTB, FTQ): split FTB meta SRAM and FTQ meta SRAM #4360

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4b86cb0
(FTB, FTQ): split ftb meta SRAM and ftq meta SRAM
TheKiteRunner24 Mar 4, 2025
67e0966
Merge branch 'master' into ftb-sram-split
TheKiteRunner24 Mar 12, 2025
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6 changes: 4 additions & 2 deletions src/main/scala/xiangshan/frontend/FTB.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@ package xiangshan.frontend

import chisel3._
import chisel3.util._
import coupledL2.utils.SplittedSRAM
import org.chipsalliance.cde.config.Parameters
import scala.{Tuple2 => &}
import utility._
Expand Down Expand Up @@ -493,14 +494,15 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
})

// Extract holdRead logic to fix bug that update read override predict read result
val ftb = Module(new SRAMTemplate(
val ftb = Module(new SplittedSRAM(
new FTBEntryWithTag,
set = numSets,
way = numWays,
dataSplit = 8,
shouldReset = true,
holdRead = false,
singlePort = true,
withClockGate = true,
clockGated = true,
hasMbist = hasMbist
))
private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "MbistPipeFtb", hasMbist)
Expand Down
11 changes: 10 additions & 1 deletion src/main/scala/xiangshan/frontend/NewFtq.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@ package xiangshan.frontend

import chisel3._
import chisel3.util._
import coupledL2.utils.SplittedSRAM
import org.chipsalliance.cde.config.Parameters
import utility._
import utility.ChiselDB
Expand Down Expand Up @@ -77,7 +78,15 @@ class FtqNRSRAM[T <: Data](gen: T, numRead: Int)(implicit p: Parameters) extends
})

for (i <- 0 until numRead) {
val sram = Module(new SRAMTemplate(gen, FtqSize, withClockGate = true, hasMbist = hasMbist))
val sram = Module(new SplittedSRAM(
gen,
set = FtqSize,
way = 1,
dataSplit = 2,
singlePort = false,
clockGated = true,
hasMbist = hasMbist
))
sram.io.r.req.valid := io.ren(i)
sram.io.r.req.bits.setIdx := io.raddr(i)
io.rdata(i) := sram.io.r.resp.data(0)
Expand Down
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