fix(uncache): if can merge, it can enter even if buffer is full #10559
Triggered via pull request
March 12, 2025 09:40
Maxpicca-Li
Status
Success
Total duration
12h 21m 49s
Artifacts
3
emu.yml
on: pull_request
Changes Detection
4s
Generate Verilog
1h 43m
EMU - Basics
12h 21m
EMU - CHI
1h 14m
EMU - Performance
3h 10m
EMU - MC
12h 18m
SIMV - Basics
3h 56m
Upload Artifacts
23m 43s
Check Submodules
27s
Check Format
2m 45s
Annotations
1 warning
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Changes Detection
Unexpected input(s) 'predicate-quantifier', valid inputs are ['token', 'working-directory', 'ref', 'base', 'filters', 'list-files', 'initial-fetch-depth']
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Artifacts
Produced during runtime
| Name | Size | |
|---|---|---|
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xs-issue-b-difftest-verilog
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12.8 MB |
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xs-issue-e-b-difftest-verilog
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12.8 MB |
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xsgen
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107 MB |
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