cpu-o3: changge store misaligned warn to DPRINTF

many warning of Store misaligned because of Error path Change-Id: I6dc10ec27b5ed15178d0f1442895e50a883e56b1
OpenXiangShan · Jan 21, 2025 · 7c59164 · 7c59164
1 parent fa6ff8d
commit 7c59164
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
@@ -1035,7 +1035,7 @@ LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
     inst->effSize = size;
 
     if (!isLoad && !inst->isVector() && size > 1 && addr % size != 0) {
-        warn( "Store misaligned: size: %u, Addr: %#lx, code: %d\n", size,
+         DPRINTF(LSQ, "Store misaligned: size: %u, Addr: %#lx, code: %d\n", size,
             addr, RiscvISA::ExceptionCode::STORE_ADDR_MISALIGNED);
         return std::make_shared<RiscvISA::AddressFault>(request->mainReq()->getVaddr(),
             request->mainReq()->getgPaddr(),