EFUSE TX-power port + cross-validation oracle + 4 init-drift bug fixes (T1)

README.md

@@ -4,12 +4,13 @@ The Realtek 11ac driver that simply devours its competitors.
 
 Devourer is a userspace re-implementation of Realtek's RTL88xxAU Wi-Fi
 driver (Jaguar family: RTL8812AU shipping on every band/channel,
-RTL8821AU shipping at 2.4 GHz and 5 GHz UNII-1 RX, RTL8811AU supported
-via the 8812 code path, RTL8814AU RX-only), speaking to the chip
-directly through libusb. No kernel module, no `rtl8812au` DKMS tree —
-just a C++20 static library (`WiFiDriver`) plus two demo executables
-for RX and TX. It is the OpenIPC project's driver of choice for
-long-range video links built on top of cheap Realtek 11ac USB radios.
+RTL8821AU shipping on every band with partial-receiver-dependent 5 GHz
+UNII-2/3 TX, RTL8811AU supported via the 8812 code path, RTL8814AU
+RX-only), speaking to the chip directly through libusb. No kernel
+module, no `rtl8812au` DKMS tree — just a C++20 static library
+(`WiFiDriver`) plus two demo executables for RX and TX. It is the
+OpenIPC project's driver of choice for long-range video links built on
+top of cheap Realtek 11ac USB radios.
 
 ## Hardware landscape
 
@@ -26,7 +27,7 @@ layered on top.
 | **RTL8812AU**  | 2T2R            | TX + RX       | TX + RX                | TX + RX                | VID/PID `0bda:8812`; reference part — works on every channel/band combo |
 | **RTL8811AU**  | 1T1R            | TX + RX       | TX + RX                | TX + RX                | 1T1R cut of 8812 silicon; rides 8812 code path with `RFType=RF_TYPE_1T1R` selected from `REG_SYS_CFG` bit 27. Status mirrored from 8812 — no 8811AU DUT in the test rig |
 | **RTL8814AU**  | 4T4R, 3-SS max  | RX only       | RX only                | RX only                | VID/PID `0bda:8813`; 2-SS effective on USB-2. TX submits succeed on the bulk pipe but nothing reaches the air at any band — see issue #36 |
-| **RTL8821AU**  | 1T1R AC + BT    | TX + RX       | RX only                | none                   | OEM-rebadged as TP-Link Archer T2U Plus (`2357:0120`) etc; Android hotplug works end-to-end. 5 GHz UNII-1 RX works on this chip but TX is silently gated — sweep `--channel 36/40/44/48` to verify on your hardware. UNII-2 / UNII-3 (ch100, 149, 161, …) are completely broken — both TX and RX. Five hypotheses tested + refuted to date (IQK port, BB-divergence overrides, missing init writes, post-channel-set delay, TX power cap) — see issue #59 |
+| **RTL8821AU**  | 1T1R AC + BT    | TX + RX       | TX + RX                | TX (receiver-dependent) + RX (receiver-dependent) | OEM-rebadged as TP-Link Archer T2U Plus (`2357:0120`) etc; Android hotplug works end-to-end. 5 GHz UNII-1 TX validated against both 8812AU and 8814AU receivers post-T1 EFUSE per-rate TX-power port. UNII-2/3 (ch100+): TX reaches the air at full rate when received by an 8814AU peer (matrix at ch100 shows 4160/4500 hits) but is dropped by an 8812AU peer; RX path on 8821AU itself is broken at UNII-2/3 (kernel-TX → 8821-devourer-RX = 0 hits at ch100+). Six hypotheses tested + refuted for the residual UNII-2/3 RX gate and 8812-RX-side asymmetry — see issue #59 |
 
 Successor families (`Jaguar2` / `Jaguar+` — 8812BU, 8822BU/BE, etc., and
 the later `Kestrel` 11ax generation) are **out of scope**: they share

hal/Hal8812a_PhyRegPg.h

@@ -0,0 +1,71 @@
+#ifndef HAL_8812A_PHY_REG_PG_H
+#define HAL_8812A_PHY_REG_PG_H
+
+#include <cstdint>
+
+/* Verbatim copy of `array_mp_8812a_phy_reg_pg` from
+ * aircrack-ng/rtl8812au@v5.6.4.2_35491.20191025
+ * hal/phydm/rtl8812a/halhwimg8812a_bb.c:1012-1058.
+ *
+ * Per-rate TX-power table. Each row is 6 entries:
+ *   {band, rfpath, tx_num, addr, bitmask, data}
+ * - band: 0 = 2.4G, 1 = 5G
+ * - rfpath: 0 = A, 1 = B
+ * - tx_num: 0 = 1T, 1 = 2T
+ * - addr: target BB register (e.g. 0xc24 = OFDM 18/6 power),
+ *         each byte of `data` is the raw power index for one rate
+ * - bitmask: 0xffffffff for the full 4-byte target
+ * - data: 4 packed bytes — per-rate target value, parsed by
+ *         `EepromManager::LoadTxPowerByRate` into
+ *         `TxPwrByRateOffset[band][path][rate]`. */
+
+static const uint32_t kHal8812aPhyRegPg[] = {
+	0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840,
+	0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
+	0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638,
+	0, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444,
+	0, 0, 0, 0x00000c30, 0xffffffff, 0x28303236,
+	0, 0, 1, 0x00000c34, 0xffffffff, 0x38404242,
+	0, 0, 1, 0x00000c38, 0xffffffff, 0x26283034,
+	0, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444,
+	0, 0, 0, 0x00000c40, 0xffffffff, 0x28303236,
+	0, 0, 0, 0x00000c44, 0xffffffff, 0x42422426,
+	0, 0, 1, 0x00000c48, 0xffffffff, 0x30343840,
+	0, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
+	0, 1, 0, 0x00000e20, 0xffffffff, 0x34363840,
+	0, 1, 0, 0x00000e24, 0xffffffff, 0x42424444,
+	0, 1, 0, 0x00000e28, 0xffffffff, 0x30323638,
+	0, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444,
+	0, 1, 0, 0x00000e30, 0xffffffff, 0x28303236,
+	0, 1, 1, 0x00000e34, 0xffffffff, 0x38404242,
+	0, 1, 1, 0x00000e38, 0xffffffff, 0x26283034,
+	0, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444,
+	0, 1, 0, 0x00000e40, 0xffffffff, 0x28303236,
+	0, 1, 0, 0x00000e44, 0xffffffff, 0x42422426,
+	0, 1, 1, 0x00000e48, 0xffffffff, 0x30343840,
+	0, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628,
+	1, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
+	1, 0, 0, 0x00000c28, 0xffffffff, 0x30323640,
+	1, 0, 0, 0x00000c2c, 0xffffffff, 0x40424444,
+	1, 0, 0, 0x00000c30, 0xffffffff, 0x28303236,
+	1, 0, 1, 0x00000c34, 0xffffffff, 0x38404242,
+	1, 0, 1, 0x00000c38, 0xffffffff, 0x26283034,
+	1, 0, 0, 0x00000c3c, 0xffffffff, 0x40424444,
+	1, 0, 0, 0x00000c40, 0xffffffff, 0x28303236,
+	1, 0, 0, 0x00000c44, 0xffffffff, 0x42422426,
+	1, 0, 1, 0x00000c48, 0xffffffff, 0x30343840,
+	1, 0, 1, 0x00000c4c, 0xffffffff, 0x22242628,
+	1, 1, 0, 0x00000e24, 0xffffffff, 0x42424444,
+	1, 1, 0, 0x00000e28, 0xffffffff, 0x30323640,
+	1, 1, 0, 0x00000e2c, 0xffffffff, 0x40424444,
+	1, 1, 0, 0x00000e30, 0xffffffff, 0x28303236,
+	1, 1, 1, 0x00000e34, 0xffffffff, 0x38404242,
+	1, 1, 1, 0x00000e38, 0xffffffff, 0x26283034,
+	1, 1, 0, 0x00000e3c, 0xffffffff, 0x40424444,
+	1, 1, 0, 0x00000e40, 0xffffffff, 0x28303236,
+	1, 1, 0, 0x00000e44, 0xffffffff, 0x42422426,
+	1, 1, 1, 0x00000e48, 0xffffffff, 0x30343840,
+	1, 1, 1, 0x00000e4c, 0xffffffff, 0x22242628
+};
+
+#endif /* HAL_8812A_PHY_REG_PG_H */