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Fix reset #212

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Fix reset #212

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4ebd338
Merge pull request #206 from zhangziqing/oscpu-master-wip
poemonsense Aug 26, 2024
34fc5cf
Fixed the bug where the Queue still allowed entries when reset or flu…
Oct 26, 2024
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9 changes: 8 additions & 1 deletion src/main/scala/utils/FlushableQueue.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,8 @@ class FlushableQueue[T <: Data](gen: T, val entries: Int,
private val full = ptr_match && maybe_full
private val do_enq = WireInit(io.enq.fire)
private val do_deq = WireInit(io.deq.fire)
//Unable enter quene when reset or flush
private val not_enq = RegInit(true.B)

when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
Expand All @@ -43,7 +45,7 @@ class FlushableQueue[T <: Data](gen: T, val entries: Int,
}

io.deq.valid := !empty
io.enq.ready := !full
io.enq.ready := !full & !not_enq
io.deq.bits := ram(deq_ptr.value)

if (flow) {
Expand All @@ -65,6 +67,11 @@ class FlushableQueue[T <: Data](gen: T, val entries: Int,
deq_ptr.value := 0.U
}
maybe_full := false.B
not_enq := true.B
}

when (!io.flush){
not_enq := false.B //add
}

private val ptr_diff = enq_ptr.value - deq_ptr.value
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14 changes: 10 additions & 4 deletions src/main/scala/utils/SRAMTemplate.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -74,17 +74,23 @@ class SRAMTemplate[T <: Data](gen: T, set: Int, way: Int = 1,

val wordType = UInt(gen.getWidth.W)
val array = SyncReadMem(set, Vec(way, wordType))
val (resetState, resetSet) = (WireInit(false.B), WireInit(0.U))
val (resetState, resetSet) = (RegInit(false.B), WireInit(0.U))

if (shouldReset) {
val _resetState = RegInit(true.B)
val (_resetSet, resetFinish) = Counter(_resetState, set)
when (resetFinish) { _resetState := false.B }
val (_resetSet, resetFinish) = Counter(resetState, set)
when (resetFinish) { _resetState := false.B;resetState := false.B }

resetState := _resetState
resetSet := _resetSet

withReset(reset.asBool){
when(!reset.asBool) {
resetState := _resetState
}
}

}

val (ren, wen) = (io.r.req.valid, io.w.req.valid || resetState)
val realRen = (if (singlePort) ren && !wen else ren)

Expand Down