545.29.02

CHANGELOG.md

@@ -2,6 +2,8 @@
 
 ## Release 545 Entries
 
+### [545.29.02] 2023-10-31
+
 ### [545.23.06] 2023-10-17
 
 #### Fixed
@@ -62,6 +64,10 @@
 
 ## Release 525 Entries
 
+#### Fixed
+
+- Fix nvidia_p2p_get_pages(): Fix double-free in register-callback error path, [#557](https://github.com/NVIDIA/open-gpu-kernel-modules/pull/557) by @BrendanCunningham
+
 ### [525.116.04] 2023-05-09
 
 ### [525.116.03] 2023-04-25

README.md

@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source
 
 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 545.23.06.
+version 545.29.02.
 
 
 ## How to Build
@@ -17,7 +17,7 @@ as root:
 
 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-545.23.06 driver release.  This can be achieved by installing
+545.29.02 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,
 
@@ -188,7 +188,7 @@ encountered specific to them.
 For details on feature support and limitations, see the NVIDIA GPU driver
 end user README here:
 
-https://us.download.nvidia.com/XFree86/Linux-x86_64/545.23.06/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/545.29.02/README/kernel_open.html
 
 In the below table, if three IDs are listed, the first is the PCI Device 
 ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
@@ -658,13 +658,15 @@ Subsystem Device ID.
 | NVIDIA A100-SXM4-80GB                           | 20B2 10DE 147F |
 | NVIDIA A100-SXM4-80GB                           | 20B2 10DE 1622 |
 | NVIDIA A100-SXM4-80GB                           | 20B2 10DE 1623 |
+| NVIDIA PG509-210                                | 20B2 10DE 1625 |
 | NVIDIA A100-SXM-64GB                            | 20B3 10DE 14A7 |
 | NVIDIA A100-SXM-64GB                            | 20B3 10DE 14A8 |
 | NVIDIA A100 80GB PCIe                           | 20B5 10DE 1533 |
 | NVIDIA A100 80GB PCIe                           | 20B5 10DE 1642 |
 | NVIDIA PG506-232                                | 20B6 10DE 1492 |
 | NVIDIA A30                                      | 20B7 10DE 1532 |
 | NVIDIA A30                                      | 20B7 10DE 1804 |
+| NVIDIA A30                                      | 20B7 10DE 1852 |
 | NVIDIA A800-SXM4-40GB                           | 20BD 10DE 17F4 |
 | NVIDIA A100-PCIE-40GB                           | 20F1 10DE 145F |
 | NVIDIA A800-SXM4-80GB                           | 20F3 10DE 179B |
@@ -748,6 +750,8 @@ Subsystem Device ID.
 | NVIDIA H100 PCIe                                | 2331 10DE 1626 |
 | NVIDIA H100                                     | 2339 10DE 17FC |
 | NVIDIA H800 NVL                                 | 233A 10DE 183A |
+| GH200 120GB                                     | 2342 10DE 16EB |
+| GH200 480GB                                     | 2342 10DE 1809 |
 | NVIDIA GeForce RTX 3060 Ti                      | 2414           |
 | NVIDIA GeForce RTX 3080 Ti Laptop GPU           | 2420           |
 | NVIDIA RTX A5500 Laptop GPU                     | 2438           |

kernel-open/Kbuild

@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
 EXTRA_CFLAGS += -I$(src)
 EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
 EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
-EXTRA_CFLAGS += -DNV_VERSION_STRING=\"545.23.06\"
+EXTRA_CFLAGS += -DNV_VERSION_STRING=\"545.29.02\"
 
 ifneq ($(SYSSRCHOST1X),)
  EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

kernel-open/nvidia-drm/nvidia-drm-drv.c

@@ -729,22 +729,28 @@ static int nv_drm_get_dev_info_ioctl(struct drm_device *dev,
 
     params->gpu_id = nv_dev->gpu_info.gpu_id;
     params->primary_index = dev->primary->index;
+    params->supports_alloc = false;
     params->generic_page_kind = 0;
     params->page_kind_generation = 0;
     params->sector_layout = 0;
     params->supports_sync_fd = false;
     params->supports_semsurf = false;
 
 #if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
-    params->generic_page_kind = nv_dev->genericPageKind;
-    params->page_kind_generation = nv_dev->pageKindGeneration;
-    params->sector_layout = nv_dev->sectorLayout;
-    /* Semaphore surfaces are only supported if the modeset = 1 parameter is set */
-    if ((nv_dev->pDevice) != NULL && (nv_dev->semsurf_stride != 0)) {
-        params->supports_semsurf = true;
+    /* Memory allocation and semaphore surfaces are only supported
+     * if the modeset = 1 parameter is set */
+    if (nv_dev->pDevice != NULL) {
+        params->supports_alloc = true;
+        params->generic_page_kind = nv_dev->genericPageKind;
+        params->page_kind_generation = nv_dev->pageKindGeneration;
+        params->sector_layout = nv_dev->sectorLayout;
+
+        if (nv_dev->semsurf_stride != 0) {
+            params->supports_semsurf = true;
 #if defined(NV_SYNC_FILE_GET_FENCE_PRESENT)
-        params->supports_sync_fd = true;
+            params->supports_sync_fd = true;
 #endif /* defined(NV_SYNC_FILE_GET_FENCE_PRESENT) */
+        }
     }
 #endif /* defined(NV_DRM_ATOMIC_MODESET_AVAILABLE) */
 

kernel-open/nvidia-drm/nvidia-drm-ioctl.h

@@ -178,7 +178,10 @@ struct drm_nvidia_get_dev_info_params {
     uint32_t gpu_id;             /* OUT */
     uint32_t primary_index;      /* OUT; the "card%d" value */
 
-    /* See DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D definitions of these */
+    uint32_t supports_alloc;     /* OUT */
+    /* The generic_page_kind, page_kind_generation, and sector_layout
+     * fields are only valid if supports_alloc is true.
+     * See DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D definitions of these. */
     uint32_t generic_page_kind;    /* OUT */
     uint32_t page_kind_generation; /* OUT */
     uint32_t sector_layout;        /* OUT */

kernel-open/nvidia/nv-msi.c

@@ -156,7 +156,7 @@ NvS32 NV_API_CALL nv_request_msix_irq(nv_linux_state_t *nvl)
         {
             for( j = 0; j < i; j++)
             {
-                free_irq(nvl->msix_entries[i].vector, (void *)nvl);
+                free_irq(nvl->msix_entries[j].vector, (void *)nvl);
             }
             break;
         }

kernel-open/nvidia/nv-p2p.c

@@ -506,8 +506,13 @@ static int nv_p2p_get_pages(
     (*page_table)->page_size = page_size_index;
 
     os_free_mem(physical_addresses);
+    physical_addresses = NULL;
+
     os_free_mem(wreqmb_h);
+    wreqmb_h = NULL;
+
     os_free_mem(rreqmb_h);
+    rreqmb_h = NULL;
 
     if (free_callback != NULL)
     {

src/common/displayport/src/dp_deviceimpl.cpp

@@ -2068,11 +2068,13 @@ void DeviceImpl::setDscDecompressionDevice(bool bDscCapBasedOnParent)
                     }
                 }
             }
-            else if (this->parent && this->parent->isDSCDecompressionSupported())
+            else if (this->parent && this->parent->isDSCDecompressionSupported() &&
+                     !(this->isLogical()))
             {
                 //
                 // This condition takes care of sink devices not capable of DSC
-                // but parent is capable of DSC decompression.
+                // but parent is capable of DSC decompression. We need to skip this
+                // if sink is at logical port.
                 //
                 this->bDSCPossible = true;
                 this->devDoingDscDecompression = this->parent;

src/common/inc/nvBldVer.h

@@ -36,25 +36,25 @@
 // and then checked back in. You cannot make changes to these sections without
 // corresponding changes to the buildmeister script
 #ifndef NV_BUILD_BRANCH
-    #define NV_BUILD_BRANCH             r545_74
+    #define NV_BUILD_BRANCH             r545_96
 #endif
 #ifndef NV_PUBLIC_BRANCH
-    #define NV_PUBLIC_BRANCH             r545_74
+    #define NV_PUBLIC_BRANCH             r545_96
 #endif
 
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r545/r545_74-96"
-#define NV_BUILD_CHANGELIST_NUM         (33409679)
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r545/r545_96-120"
+#define NV_BUILD_CHANGELIST_NUM         (33457372)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r545/r545_74-96"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33409679)
+#define NV_BUILD_NAME                   "rel/gpu_drv/r545/r545_96-120"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33457372)
 
 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r545_74-8"
-#define NV_BUILD_CHANGELIST_NUM         (33409679)
+#define NV_BUILD_BRANCH_VERSION         "r545_96-2"
+#define NV_BUILD_CHANGELIST_NUM         (33457372)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "545.87"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33409679)
+#define NV_BUILD_NAME                   "546.01"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33457372)
 #define NV_BUILD_BRANCH_BASE_VERSION    R545
 #endif
 // End buildmeister python edited section

src/common/inc/nvUnixVersion.h

@@ -4,7 +4,7 @@
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
     (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
 
-#define NV_VERSION_STRING               "545.23.06"
+#define NV_VERSION_STRING               "545.29.02"
 
 #else
 

src/common/sdk/nvidia/inc/ctrl/ctrl30f1.h

@@ -887,10 +887,6 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS {
  *   This parameter is set by the client to indicate the 
  *   gpuId of the GPU to which the display to be optimized
  *   is attached.
- * display
- *   This parameter is not used by RM currently.
- *   Clients can ignore this parameter.  Note that this
- *   parameter will be removed in future.
  * output
  *   This parameter is set by the client to indicate the 
  *   output resource type of the display to be optimized.
@@ -1033,6 +1029,12 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS {
  *   optimal pixel clock to use with the adjusted mode, 
  *   in units of Hz. 
  *
+ *
+ * bOptimized[out]
+ *   This is set to NV_TRUE if the timings were successfully optimized, and
+ *   NV_FALSE otherwise.
+ *
+ *
  * Progressive Raster Structure
  *
  *                 hSyncEnd                            hTotal
@@ -1145,28 +1147,29 @@ typedef struct NV30F1_CTRL_GSYNC_GET_CONTROL_SWAP_LOCK_WINDOW_PARAMS {
 #define NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS_MESSAGE_ID (0x60U)
 
 typedef struct NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS {
-    NvU32 gpuId;
-    NvU32 display;
-    NvU32 output;
-    NvU32 protocol;
-    NvU32 structure;
-    NvU32 adjust;
-    NvU32 hDeltaStep;
-    NvU32 hDeltaMax;
-    NvU32 vDeltaStep;
-    NvU32 vDeltaMax;
-    NvU32 hSyncEnd;
-    NvU32 hBlankEnd;
-    NvU32 hBlankStart;
-    NvU32 hTotal;
-    NvU32 vSyncEnd;
-    NvU32 vBlankEnd;
-    NvU32 vBlankStart;
-    NvU32 vInterlacedBlankEnd;
-    NvU32 vInterlacedBlankStart;
-    NvU32 vTotal;
-    NvU32 refreshX10K;
-    NvU32 pixelClockHz;
+    NvU32  gpuId;
+    NvU32  output;
+    NvU32  protocol;
+    NvU32  structure;
+    NvU32  adjust;
+    NvU32  hDeltaStep;
+    NvU32  hDeltaMax;
+    NvU32  vDeltaStep;
+    NvU32  vDeltaMax;
+    NvU32  hSyncEnd;
+    NvU32  hBlankEnd;
+    NvU32  hBlankStart;
+    NvU32  hTotal;
+    NvU32  vSyncEnd;
+    NvU32  vBlankEnd;
+    NvU32  vBlankStart;
+    NvU32  vInterlacedBlankEnd;
+    NvU32  vInterlacedBlankStart;
+    NvU32  vTotal;
+    NvU32  refreshX10K;
+    NvU32  pixelClockHz;
+
+    NvBool bOptimized;
 } NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS;
 
 /* output values */

src/nvidia-modeset/src/nvkms-evo.c

@@ -786,6 +786,9 @@ static void TweakTimingsForGsync(const NVDpyEvoRec *pDpyEvo,
             return;
     }
 
+    nvEvoLogInfoString(pInfoString,
+            "Adjusting Mode Timings for Quadro Sync Compatibility");
+
     ret = nvRmApiControl(nvEvoGlobal.clientHandle,
                          pDispEvo->pFrameLockEvo->device,
                          NV30F1_CTRL_CMD_GSYNC_GET_OPTIMIZED_TIMING,
@@ -796,12 +799,13 @@ static void TweakTimingsForGsync(const NVDpyEvoRec *pDpyEvo,
         nvAssert(!"Failed to convert to Quadro Sync safe timing");
         /* do not apply the timings returned by RM if the call failed */
         return;
+    } else if (!gsyncOptTimingParams.bOptimized) {
+        nvEvoLogInfoString(pInfoString, " Timings Unchanged.");
+        return;
     }
 
     nvConstructNvModeTimingsFromHwModeTimings(pTimings, &modeTimings);
 
-    nvEvoLogInfoString(pInfoString,
-            "Adjusting Mode Timings for Quadro Sync Compatibility");
     nvEvoLogInfoString(pInfoString, " Old Timings:");
     nvEvoLogModeValidationModeTimings(pInfoString, &modeTimings);
 
@@ -5923,13 +5927,6 @@ NvBool nvConstructHwModeTimingsImpCheckEvo(
                                   NVKMS_MODE_VALIDATION_REQUIRE_BOOT_CLOCKS);
     NvU32 ret;
 
-    /* bypass this checking if the user disabled IMP */
-
-    if ((pParams->overrides &
-         NVKMS_MODE_VALIDATION_NO_EXTENDED_GPU_CAPABILITIES_CHECK) != 0) {
-        return TRUE;
-    }
-
     activeRmId = nvRmAllocDisplayId(pConnectorEvo->pDispEvo,
                     nvAddDpyIdToEmptyDpyIdList(pConnectorEvo->displayId));
     if (activeRmId == 0x0) {
@@ -5954,11 +5951,18 @@ NvBool nvConstructHwModeTimingsImpCheckEvo(
         timingsParams[head].pUsage = &timings[head].viewPort.guaranteedUsage;
     }
 
-    ret = nvValidateImpOneDispDowngrade(pConnectorEvo->pDispEvo, timingsParams,
-                                        requireBootClocks,
-                                        NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE,
-                                        /* downgradePossibleHeadsBitMask */
-                                        (NVBIT(NVKMS_MAX_HEADS_PER_DISP) - 1UL));
+    /* bypass this checking if the user disabled IMP */
+    if ((pParams->overrides &
+         NVKMS_MODE_VALIDATION_NO_EXTENDED_GPU_CAPABILITIES_CHECK) != 0) {
+        ret = TRUE;
+    } else {
+        ret = nvValidateImpOneDispDowngrade(pConnectorEvo->pDispEvo, timingsParams,
+                                            requireBootClocks,
+                                            NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE,
+                                            /* downgradePossibleHeadsBitMask */
+                                            (NVBIT(NVKMS_MAX_HEADS_PER_DISP) - 1UL));
+    }
+
     if (ret) {
         *pNumHeads = numHeads;
     } else {

src/nvidia/generated/g_nv_name_released.h

@@ -808,13 +808,15 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x20B2, 0x147f, 0x10de, "NVIDIA A100-SXM4-80GB" },
     { 0x20B2, 0x1622, 0x10de, "NVIDIA A100-SXM4-80GB" },
     { 0x20B2, 0x1623, 0x10de, "NVIDIA A100-SXM4-80GB" },
+    { 0x20B2, 0x1625, 0x10de, "NVIDIA PG509-210" },
     { 0x20B3, 0x14a7, 0x10de, "NVIDIA A100-SXM-64GB" },
     { 0x20B3, 0x14a8, 0x10de, "NVIDIA A100-SXM-64GB" },
     { 0x20B5, 0x1533, 0x10de, "NVIDIA A100 80GB PCIe" },
     { 0x20B5, 0x1642, 0x10de, "NVIDIA A100 80GB PCIe" },
     { 0x20B6, 0x1492, 0x10de, "NVIDIA PG506-232" },
     { 0x20B7, 0x1532, 0x10de, "NVIDIA A30" },
     { 0x20B7, 0x1804, 0x10de, "NVIDIA A30" },
+    { 0x20B7, 0x1852, 0x10de, "NVIDIA A30" },
     { 0x20BD, 0x17f4, 0x10de, "NVIDIA A800-SXM4-40GB" },
     { 0x20F1, 0x145f, 0x10de, "NVIDIA A100-PCIE-40GB" },
     { 0x20F3, 0x179b, 0x10de, "NVIDIA A800-SXM4-80GB" },
@@ -899,6 +901,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
     { 0x2331, 0x1626, 0x10de, "NVIDIA H100 PCIe" },
     { 0x2339, 0x17fc, 0x10de, "NVIDIA H100" },
     { 0x233A, 0x183a, 0x10de, "NVIDIA H800 NVL" },
+    { 0x2342, 0x16eb, 0x10de, "GH200 120GB" },
+    { 0x2342, 0x1809, 0x10de, "GH200 480GB" },
     { 0x2414, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Ti" },
     { 0x2420, 0x0000, 0x0000, "NVIDIA GeForce RTX 3080 Ti Laptop GPU" },
     { 0x2438, 0x0000, 0x0000, "NVIDIA RTX A5500 Laptop GPU" },