Experimental std::simd

[fbusato]

Motivations

Modern GPU architectures are increasingly exposing fine-grained, single-thread SIMD capabilities to maximize throughput within individual CUDA threads. While GPU programming model strongly focuses on the SIMT model, newer hardware relies on specialized SIMD operations to saturate execution units. Some examples include:

• int16_t SIMD instructions DPX.
• FADDx2, FMULx2, FMAx2.
• Bfloat16x2 and Halfx2 intrinsics.
• 3-Input floating-point Minimum / Maximum.
• Integer Add X3 (IADD3).
• Integer dot product __dp4a.
• SIMD Video Instructions, e.g. vabsdiff4.
• SIMD within a register (SWAR) for integer types

C++26 std::simd provides a standardized abstraction to write vectorized code. This is a great opportunity to unify customized code to handle all variants and reduce CUDA software fragmentation. By adopting std::simd-like API, developers can write a single vectorized kernel that compiles to the optimal instructions for any GPU architecture.

PR Goals and Non-Goals

The PR aims to provide a basic implementation of std::simd and provide the foundation for future optimizations and extensions.

Advanced math and bit operations, e.g. std::abs , std::pow, std::popcount etc. , as well as std::complex binding, are outside the scope of the first PR.

Non-Goals:

• Fully-implement std::simd.
• Implement custom ABIs to target host vector instructions.

Implementation Notes

The implementation is based on the LLVM code experimental/__simd and extended to support the related C++ proposals:

• std::simd — merge data -parallel types from the Parallelism TS 2.
• simd issues: explicit, unsequenced, identity-element position, and members of disabled simd
• Exploration of namespaces for std::simd

Some optimizations are already exploited in the CCCL code, for example thread_simd.h and thread_reduce.h. They will gradually added to the implementation.

Partially address #30

[miscco]

This is not using SIMD on the host, is there any reason for that?

[fbusato]

because this is the first PR. Secondly, because we care more about GPU than CPU. Third, the feature is also experimental for other std libraries.

[mhoemmen]

Per offline discussion, Federico will first update to the latest draft N5032 ( https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2025/n5032.pdf ).

[mhoemmen]

WG21 adopted P3691R1 at the June 2025 Sofia meeting. This renamed the namespace to "simd" and renamed the data types basic_mask / mask and basic_vec / vec.

[mhoemmen]

[simd] does not declare any public namespaces other than std::simd.

[mhoemmen]

native-abi is exposition-only (see [simd.expos.abi]). The others don't appear to be named at all in [simd].

[mhoemmen]

The synopsis declares basic_vec like this, where @_X_@ indicates italic code-font X (meaning that it's an exposition-only name).

template<class T, class Abi = @_native-abi_@<T>> class basic_vec;
  template<class T, @_simd-size-type_@ N = @_simd-size-v_@<T, @_native-abi_@<T>>>
    using vec = basic_vec<T, @_deduce-abi-t_@<T, N>>;

[github-actions]

😬 CI Workflow Results

🟥 Finished in 16m 54s: Pass: 12%/48 | Total: 5h 17m | Max: 16m 27s | Hits: 99%/1356

See results here.

[fbusato]

this PR has been replaced by

• cuda::std::simd core functionalities #8251
• cuda::std::simd load and store functionalities #8252
• cuda::std::simd Reduction functionalities #8253