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Shifts and Rots
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@MichaHofft
MichaHofft committed Oct 5, 2018
1 parent 6c0358d commit c8206e4
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Showing 9 changed files with 519 additions and 256 deletions.
4 changes: 4 additions & 0 deletions .gitignore
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mini.lst
mini.rom
mini.rom.trace
~$180102f_z80_ISA_overview.xlsm
4 changes: 2 additions & 2 deletions .vscode/launch.json
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Expand Up @@ -27,8 +27,8 @@
// "-a", "mini.asm",
// "-o", "mini.rom"
"-os", "$100",
"-oe", "$110",
"-ml", "16",
"-oe", "$123",
"-ml", "104",
"-e", "mini.rom"
]
},
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Binary file modified 180102f_z80_ISA_overview.xlsm
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129 changes: 119 additions & 10 deletions dizzy.py
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Expand Up @@ -1759,7 +1759,7 @@ def assembleStage1(self, fn):
# MARK?
if OPTIONS.markAtLineNo is not None:
if OPTIONS.markAtLineNo == lineno:
print("*MARK*")
print("*MARK@STAGE1*")

# tab expansion
if OPTIONS.tabWidth > 0:
Expand Down Expand Up @@ -1884,7 +1884,7 @@ def assembleStage2(self):
# MARK?
if OPTIONS.markAtLineNo is not None:
if OPTIONS.markAtLineNo == assyrec.lineno:
print("*MARK*")
print("*MARK@STAGE2*")

# any real action required
proceed = True
Expand Down Expand Up @@ -2459,10 +2459,12 @@ class SoftFunction(Enum):
RRC = 21
SLA = 22
SRA = 23
SLL = 24
SRL = 25
RRD = 26
ADD_TWO_COMPL_OP2 = 23
SRL = 24
RLD1 = 25
RLD2 = 26
RRD1 = 27
RRD2 = 28
ADD_TWO_COMPL_OP2 = 29

class SoftFlag:
NONE = 0
Expand Down Expand Up @@ -2571,10 +2573,13 @@ def performFunction(self):
v = (self.theValue[0] & andMask) & (self.theValue[1] & andMask)
if self.function == SoftFunction.XOR:
v = (self.theValue[0] & andMask) ^ (self.theValue[1] & andMask)
self.setSingleOutFlag( SoftFlag.ZERO, v == 0 )
self.setSingleOutFlag( SoftFlag.SIGN, v & 0x80 > 0 )
self.setSingleOutFlag( SoftFlag.ZERO, v == 0 )
self.setSingleOutFlag( SoftFlag.HALFCARRY, False )
# assumption according general flags chapter, described suspicous in the user manual?!
self.setSingleOutFlag( SoftFlag.PARITYOVER, v % 2 == 0 )
self.setSingleOutFlag( SoftFlag.ADDSUB, False )
self.setSingleOutFlag( SoftFlag.CARRY, False )
return v & andMask

if self.function == SoftFunction.RLCA or self.function == SoftFunction.RLA or \
Expand Down Expand Up @@ -2610,9 +2615,85 @@ def performFunction(self):
# if not the "..A" functions, extended flag checks are made
if self.function == SoftFunction.RLC or self.function == SoftFunction.RL or \
self.function == SoftFunction.RRC or self.function == SoftFunction.RR:
self.setSingleOutFlag( SoftFlag.PARITYOVER, v > 127 or v < -128 )
self.setSingleOutFlag( SoftFlag.PARITYOVER, v % 2 == 0 )
self.setSingleOutFlag( SoftFlag.ZERO, v == 0 )
self.setSingleOutFlag( SoftFlag.SIGN, v & 0x80 > 0 )
self.setSingleOutFlag( SoftFlag.SIGN, v > 127 or v < -128 )
return v & andMask

if self.function == SoftFunction.SLA or \
self.function == SoftFunction.SRA or \
self.function == SoftFunction.SRL:
# process values as bit patterns only of ACT input (latch index 0)
v = self.theValue[0] & andMask
if self.function == SoftFunction.SLA:
cy = v & 0x80 > 0
v = (v << 1) & andMask
if self.function == SoftFunction.SRA:
msb = v & 0x80
cy = v & 0x01 > 0
v = (v >> 1) & andMask
v = v | msb
if self.function == SoftFunction.SRL:
cy = v & 0x01 > 0
v = (v >> 1) & andMask

# only some flags affected
self.setSingleOutFlag( SoftFlag.HALFCARRY, False )
self.setSingleOutFlag( SoftFlag.ADDSUB, False )
self.setSingleOutFlag( SoftFlag.CARRY, cy )
self.setSingleOutFlag( SoftFlag.PARITYOVER, v % 2 == 0 )
self.setSingleOutFlag( SoftFlag.ZERO, v == 0 )
self.setSingleOutFlag( SoftFlag.SIGN, v > 127 or v < -128 )
return v & andMask

if self.function == SoftFunction.RLD1:
# 1st half of the RLD operation
# (HL)[7..4] <- (HL)[3..0], (HL)[3..0] <- A[3..0]
# translated (HL -> TMP -> ALU2, A -> ACT - > ALU1)
# (ALU.OUT)[7..4] <- (ALU2)[3..0], (ALU.OUT)[3..0] <- (ALU1)[3..0]
v = ((self.theValue[1] & 0x0f) << 4) | (self.theValue[0] & 0x0f)

# flags to be done in 2nd half
return v & andMask

if self.function == SoftFunction.RLD2:
# 2nd half of the RLD operation
# A[7..4] <- A[7..4], A[3..0] <- (HL)[7..4]
# translated (HL -> TMP -> ALU2, A -> ACT - > ALU1)
# (ALU.OUT)[7..4] <- (ALU1)[7..4], (ALU.OUT)[3..0] <- (ALU2)[7..4]
v = (self.theValue[0] & 0xf0) | ((self.theValue[1] & 0xf0) >> 4)

# only some flags affected
self.setSingleOutFlag( SoftFlag.HALFCARRY, False )
self.setSingleOutFlag( SoftFlag.ADDSUB, False )
self.setSingleOutFlag( SoftFlag.PARITYOVER, v % 2 == 0 )
self.setSingleOutFlag( SoftFlag.ZERO, v == 0 )
self.setSingleOutFlag( SoftFlag.SIGN, v > 127 or v < -128 )
return v & andMask

if self.function == SoftFunction.RRD1:
# 1st half of the RRD operation
# (HL)[7..4] <- A[3..0], (HL)[3..0] <- (HL)[7..4]
# translated (HL -> TMP -> ALU2, A -> ACT - > ALU1)
# (ALU.OUT)[7..4] <- (ALU1)[3..0], (ALU.OUT)[3..0] <- (ALU2)[7..4]
v = ((self.theValue[0] & 0x0f) << 4) | ((self.theValue[1] & 0xf0) >> 4)

# flags to be done in 2nd half
return v & andMask

if self.function == SoftFunction.RRD2:
# 2nd half of the RRD operation
# A[7..4] <- A[7..4], A[3..0] <- (HL)[3..0]
# translated (HL -> TMP -> ALU2, A -> ACT - > ALU1)
# (ALU.OUT)[7..4] <- (ALU1)[7..4], (ALU.OUT)[3..0] <- (ALU2)[3..0]
v = (self.theValue[0] & 0xf0) | (self.theValue[1] & 0x0f)

# only some flags affected
self.setSingleOutFlag( SoftFlag.HALFCARRY, False )
self.setSingleOutFlag( SoftFlag.ADDSUB, False )
self.setSingleOutFlag( SoftFlag.PARITYOVER, v % 2 == 0 )
self.setSingleOutFlag( SoftFlag.ZERO, v == 0 )
self.setSingleOutFlag( SoftFlag.SIGN, v > 127 or v < -128 )
return v & andMask

if self.function == SoftFunction.ADD_TWO_COMPL_OP2:
Expand Down Expand Up @@ -2759,7 +2840,7 @@ def performCycle(self, operations: str):

if OPTIONS.markAtLineNo is not None:
if self.totalCycleCount == OPTIONS.markAtLineNo:
print("*MARK*")
print("*MARK@SOFTCPU*")

# split operations
if isinstance(operations, str):
Expand Down Expand Up @@ -2903,6 +2984,34 @@ def performCycle(self, operations: str):
r['ALU'].flags = r['F'].value
r['ALU'].setFunction(SoftFunction.RR)

elif op == "ALU.OP.SLA":
r['ALU'].flags = r['F'].value
r['ALU'].setFunction(SoftFunction.SLA)

elif op == "ALU.OP.SRA":
r['ALU'].flags = r['F'].value
r['ALU'].setFunction(SoftFunction.SRA)

elif op == "ALU.OP.SRL":
r['ALU'].flags = r['F'].value
r['ALU'].setFunction(SoftFunction.SRL)

elif op == "ALU.OP.RLD1":
r['ALU'].flags = r['F'].value
r['ALU'].setFunction(SoftFunction.RLD1)

elif op == "ALU.OP.RLD2":
r['ALU'].flags = r['F'].value
r['ALU'].setFunction(SoftFunction.RLD2)

elif op == "ALU.OP.RRD1":
r['ALU'].flags = r['F'].value
r['ALU'].setFunction(SoftFunction.RRD1)

elif op == "ALU.OP.RRD2":
r['ALU'].flags = r['F'].value
r['ALU'].setFunction(SoftFunction.RRD2)

elif op == "ALU.OE":
r['DBUS'].value = r['ALU'].value
r['F'].value = r['ALU'].flags
Expand Down
2 changes: 1 addition & 1 deletion do_softcpu.bat
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@@ -1,2 +1,2 @@
@rem python dizzy.py -v -v -os $100 -oe $110 -ml 1 -e mini.rom 2>&1 | less -p MARK
python dizzy.py -v -v -os $100 -oe $110 -ml 1 -e mini.rom 2>&1 > mini.rom.trace
python dizzy.py -v -v -os $100 -oe $123 -ml 104 -e mini.rom 2>&1 > mini.rom.trace
85 changes: 80 additions & 5 deletions mini.asm
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Expand Up @@ -5,13 +5,88 @@ TFCB EQU TFCA+1
;------------------------------
ORG 100h
;
hallo: ; RRC further
LD IX,buftmp ; not a constant one
hallo: ; START
; RRD
LD HL,buftmp
LD (HL),00100000b
LD A,10000100b
RRD
LD B,(HL) ; ASSERT B = $42
LD C,A ; ASSERT C = $80
; RLD
LD HL,buftmp
LD (HL),00110001b
LD A,01111010b
RLD
LD B,(HL) ; ASSERT B = $1a
LD C,A ; ASSERT C = $73
; SRL in multiple ways
OR A ; clear carry
LD A,10001111b
SRL A
LD B,A
NOP ; ASSERT B = $47, Cy set
OR A ; clear carry
LD A,10001111b
LD HL,buftmp ; not a constant one
LD (HL),A
SRL (HL)
LD C,(HL)
NOP ; ASSERT C = $47, Cy set
OR A ; clear carry
LD A,10001111b
LD IY,buftmp ; not a constant one
LD (IY+1),A
SRL (IY+1)
LD D,(IY+1)
NOP ; ASSERT D = $47, Cy set
; SRA in multiple ways
OR A ; clear carry
LD A,10111000b
SRA A
LD B,A
NOP ; ASSERT B = $dc, Cy cleared
OR A ; clear carry
LD A,10111000b
LD HL,buftmp ; not a constant one
LD (HL),A
SRA (HL)
LD C,(HL)
NOP ; ASSERT C = $dc, Cy cleared
OR A ; clear carry
LD A,10111000b
LD IY,buftmp ; not a constant one
LD (IY+1),A
SRA (IY+1)
LD D,(IY+1)
NOP ; ASSERT D = $dc, Cy cleared
; SLA in multiple ways
OR A ; clear carry
LD A,10110001b
SLA A
LD B,A
NOP ; ASSERT B = $62, Cy set
OR A ; clear carry
LD A,10110001b
LD HL,buftmp ; not a constant one
LD (HL),A
SLA (HL)
LD C,(HL)
NOP ; ASSERT C = $62, Cy set
OR A ; clear carry
LD A,10110001b
LD IY,buftmp ; not a constant one
LD (IY+1),A
SLA (IY+1)
LD D,(IY+1)
NOP ; ASSERT D = $62, Cy set
; RRC further
LD IY,buftmp ; not a constant one
LD A,00110001b
LD (IX+3),A
LD (IY+3),A
OR A ; clears carry?
RRC (IX+3) ; shall by CY, $98
LD B,(IX+3)
RRC (IY+3) ; shall by CY, $98
LD C,(IY+3)
NOP
NOP
; RR further
Expand Down
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